CY8CTMG200-16LGXIT Cypress Semiconductor Corp, CY8CTMG200-16LGXIT Datasheet - Page 167

• Manufacturer Part Number: CY8CTMG200-16LGXIT
• Description: IC MCU 32K FLASH 16-COL
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-16LGXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 13
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The PMA's purpose is to manage the potentially conflicting
SRAM access requests from the M8C and the USB SIE.
From a performance standpoint, the PMA guarantees that a
continuous stream of move instructions (see ahead), are
serviced by the PMA without delay even while the USB SIE
is transferring data at its maximum rate in to or out of the
dedicated USB SRAM.
When servicing a request, the PMA is in one of two address-
ing modes. For M8C access the PMA always uses Post-
Increment Addressing. After a read or write request is made
to the channel's PMAx_DR register, the PMA automatically
increments the pointer into SRAM. For a read access the
next value is also automatically prefetched. For USB SIE
accesses, the PMA uses an offset addressing mode. In this
mode the channel's base address, as stored in the
PMAx_WA and PMAx_RA registers, is added to the byte
count value provided by the USB SIE.
A PMA channel does not have a defined upper limit. It is the
responsibility of the firmware to ensure that channels do not
access memory outside of the range defined by the applica-
tion.
During SIE writes to the USB SRAM, the maximum number
of bytes written is limited to the count value in the respective
endpoint's count registers. This value must be loaded by
firmware before data is received.
The rest of the description of the PMA is broken into two
parts: the M8C interface and the USB SIE interface, which
are described as follows.
PMA to M8C Interface
The M8C accesses the PMA, and thus the USB's dedicated
SRAM, by way of a register interface. Each PMA channel
has three registers associated with it as shown in
on page
instructions may be used with these registers.
MOV A, reg[expr]
MOV A, reg[X+expr]
MOV [expr], [expr]
MOV reg[expr], A
MOV reg[X+expr], A
MOV reg[expr], expr
MOV reg[X+expr], expr
When the M8C uses a PMA channel to write data into
SRAM, follow these steps:
1. Choose a PMA channel that is not allocated to a USB
2. Write the channel's PMAx_WA register with the first
3. Write data to the channel's PMAx_DR register. The PMA
While these steps are executed by the M8C, the USB SIE
may be fully active on any other PMA channel.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
endpoint, or choose a channel where the endpoint is
inactive.
address in SRAM that must be used by this channel.
logic automatically increments the PMAx_WA address
after each write.
166. Only the following basic M8C register access
Table 20-2
The M8C may also service another channel and come back
to the channel being serviced by the previous steps. To
determine the next address that is used when data is written
to the channel's PMAx_DR register, the PMAx_WA register
may be read.
When the M8C uses a PMA channel to read data from
SRAM, follow these steps:
1. Choose a PMA channel that is not allocated to a USB
2. Write the channel's PMAx_RA register with the first
3. Read data from the channel's PMAx_DR register. The
When data is read from a PMA channel the data is
prefetched; therefore, the channel must be pre-loaded prior
to the first M8C read that expects to get actual data. This
pre-loading is taken care of automatically when the
PMAx_RA register is written. This pre-loading mechanism is
actually the only difference between the PMAx_RA and
PMAx_WA registers.
PMA to USB SIE Interface
The USB SIE accesses the PMA, and thus the dedicated
USB SRAM, by way of a private interface and does not
affect the PSoC Core address or data bus. The only area of
contention that is not automatically arbitrated between the
M8C, PMA, and USB SIE are the PMAx_xx registers. When
the USB SIE is actively using a PMA channel, the M8C must
not attempt to access that channel's PMA registers. If the
M8C wants to access the same data as an active USB end-
point, the M8C must use a PMA channel separate from the
PMA channel that is permanently allocated to that endpoint.
Just as the M8C has two uses for PMA channels, read or
write, the USB SIE has two uses for a PMA channel. The
USB SIEs use of a channel may be thought of as read or
write; but, in USB terms the USB SIEs need to read data
would be associated with an IN transaction and the need to
write data with an OUT transaction.
endpoint, or choose a channel where the endpoint is
inactive.
address in SRAM that must be read by this channel.
PMA logic automatically increments the PMAx_RA
address after each read.
Full-Speed USB
167
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