CY8CTMG200-16LGXIT Cypress Semiconductor Corp, CY8CTMG200-16LGXIT Datasheet - Page 158

• Manufacturer Part Number: CY8CTMG200-16LGXIT
• Description: IC MCU 32K FLASH 16-COL
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-16LGXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 13
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Slave Select (SS_, Active Low). Slave Select must be
asserted to enable the SPIS for receive and transmit. There
are two ways to do this:
■
■
When SS_ is negated (whether from an external or internal
source), the SPIS state machine is reset and the MISO out-
put is forced to idle at logic 1. In addition, the SPIS ignores
any incoming MOSI/SCLK input from the master.
Status Generation and Interrupts. There are four status
bits in the SPIS block: TX Reg Empty, RX Reg Full, SPI
Complete, and Overrun. The timing of these status bits are
identical to the SPIM, with the exception of TX Reg Empty,
which is covered in the section on TX data queuing.
SPI
158
Drive the auxiliary input from a pin (selected by the Aux
I/O Select bits in the output register). This gives the SPI
master control of the slave selection in a multi-slave
environment.
SS_ may be controlled in firmware with register writes to
the output register. When Aux I/O Enable = 1, Aux I/O
Select bit 0 becomes the SS_ input. This allows the user
to save an input pin in single-slave environments.
TX REG EMPTY
SCLK (MODE 2)
SCLK (MODE 3)
SCLK (Internal)
RX REG FULL
Shifter is loaded with
first byte (by leading
edge of the SCLK).
byte to the TX Buffer
MISO
User writes the first
register.
Figure 18-10. Typical SPIS Timing in Modes 2 and 3
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
input bit
latched.
First
D7
Shift.
First
D6
byte to the TX Buffer
User writes the next
Last bit of received data is valid
on this edge and is latched into
Status Clear On Read. Refer to the same subsection in
SPIM Timing on page
TX Data Queuing. Most SPI applications call for data to be
sent back from the slave to the master. Writing firmware to
accomplish this requires an understanding of how the Shift
register is loaded from the TX Buffer register.
All modes use the following mechanism: 1) If there is no
transfer in progress, 2) if the shifter is empty, and 3) if data is
available in the TX Buffer register, the byte is loaded into the
shifter.
The only difference between the modes is that the definition
of “transfer in progress” is slightly different between modes 0
and 1, and modes 2 and 3.
register.
D5
the RX Buffer register.
D2
D1
152.
D0
the next byte.
loaded with
Shifter is
D7
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