CY8CTMG200-16LGXIT Cypress Semiconductor Corp, CY8CTMG200-16LGXIT Datasheet - Page 80

• Manufacturer Part Number: CY8CTMG200-16LGXIT
• Description: IC MCU 32K FLASH 16-COL
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-16LGXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 13
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.4.2
After asleep, the only event that wakes the system is an
interrupt. The Global Interrupt Enable of the CPU Flag regis-
ter does not need to be set. Any unmasked interrupt wakes
the system up. It is optional for the CPU to actually take the
interrupt after the wakeup sequence.
The wakeup sequence is synchronized to the taps from the
wakeup timer (running on IMO clock). This allows the Flash
memory module enough time to power up before the CPU
asserts the first read access. Another reason for the delay is
to allow the IMO, bandgap, and LVD/POR circuits time to
settle before actually being used in the system. As shown in
Figure
1. The wakeup interrupt occurs and the sequence is initi-
2. At T1, the bandgap is sampled and the Flash is enabled.
3. At T2, the Flash is put in power saving mode (idle).
4. At T3, the POR/LVD comparators are sampled and the
There is no difference in wakeup from deep sleep or buzzed
sleep because in all cases, in order to achieve the power
specification, the regulator, references and core blocks must
be shut off.
The buzz sequence after the Buzz signal comes. This is shown in
Sleep and Watchdog
o m s ta n d b y to B G
80
r s w itc h e s E n a b le
R e g u la to r E n a b le
S a m p le B a n d g a p
B a n d g a p E n a b le
S w itc h re fe re n c e
ated at INT (shown in
interrupt asynchronously enables the regulator, the
bandgap circuit, LSO, POR, and the IMO. As the core
power ramps, the IMO starts to oscillate and the remain-
der of the sequence is timed with configurable durations
from the wakeup timer.
CPU restarts.
S a m p le P O R
P O R E n a b le
IM O E n a b le
10-2, the wakeup sequence is as follows.
B U Z Z
Wakeup Sequence
B U Z Z
Figure 10-2 on page
P o w e r g o o d
T 0
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Figure 10-4. Buzz Sequence Timing
75). The
1 0 -3 0 u s
10.4.3
During normal operation the bandgap circuit provides a volt-
age reference (VRef) to the system for use in the analog
blocks, Flash, and low voltage detect (LVD) circuitry. Nor-
mally, the bandgap output is connected directly to the VRef
signal. However, during sleep, the bandgap reference gen-
erator block and LVD circuits are completely powered down.
The bandgap and LVD blocks are periodically reenabled
during sleep to monitor for low voltage conditions. This is
accomplished by periodically turning on the bandgap.
The rate at which the refresh occurs is related to the 32 kHz
clock and controlled by the Power System Sleep Duty Cycle.
Table 10-1
Table 10-1. Power System Sleep Duty Cycle Selections
00b (default)
01b
10b
11b
Note Valid when ALT_Buzz[1:0] of the SLP_CFG2 register is 00b.
Figure 10-4, “Buzz Sequence Timing,” on page
T 1
PSSDC
lists the available selections.
3 -1 0 u s
Bandgap Refresh
64
256
1024
16
Sleep Timer Counts
T 2
1 -1 0 u s
T 3
2 IM O
c y c le s
8 ms
31.2 ms
2 ms
500 µs
Period (Nominal)
T 4
80.
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