CY8CTMG200-16LGXIT Cypress Semiconductor Corp, CY8CTMG200-16LGXIT Datasheet - Page 161

• Manufacturer Part Number: CY8CTMG200-16LGXIT
• Description: IC MCU 32K FLASH 16-COL
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-16LGXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 13
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

This chapter presents the Programmable Timer and its associated registers. For a complete table of the programmable timer
registers, refer to the
isters in address order, refer to the
19.1
The device has three programmable timers (TIMER0,
TIMER1, TIMER2). All three timers are individually con-
trolled. The programmable timers are 16-bit down counters
for the device. TIMER0 has a terminal count output. The tim-
ers have one configuration and two data registers associ-
ated with them. You start these timers by setting the START
bit in their configuration registers (PT0_CFG, PT1_CFG,
PT2_CFG). When started, the timers always start counting
down from the value loaded into their data registers
(PT*_DATA1, PT*_DATA0). The timers have a one-shot
mode, in which the timers complete one full count cycle and
stop. In one-shot mode the START bit in the configuration
register is cleared after completion of one full count cycle.
Setting the START bit restarts the timer.
Figure 19-1. Programmable Timer Block Diagram
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
19. Programmable Timer
32 kHz
Clock/ CPU
Clock
Architectural Description
CONFIGURATION[7:0]
Summary Table of the System Resource Registers on page
Programmable
Registers
DATA[7:0]
DATA[7:0]
Timer
Register Reference chapter on page
Terminal
Count
19.1.1
When started, the programmable timer loads the value con-
tained in its data registers and counts down to its terminal
count of zero. The timers output an active high terminal
count pulse for one clock cycle upon reaching the terminal
count. The low time of the terminal count pulse is equal to
the loaded decimal count value, multiplied by the clock
period (TC
period of the terminal count output is the pulse width of the
terminal count, plus one clock period (TC
CLK
Only TIMER0 outputs this terminal count output. TIMER1
and TIMER2 do not have a terminal count output.
The timers work on either the 32 kHz clock or CPU clock.
This clock selection is done using the CLKSEL bits in the
respective configuration registers (PT0_CFG, PT1_CFG,
PT2_CFG). Make clock selections before setting the START
bit so that the timing is not affected and clock frequency
does not change while the timer is running.
TIMER1 works on prescaled IMO clock (IMO-P) when the
CSD_MODE bit in the CS_CR0 (0,A0) register is set to ‘1’.
TIMER1 outputs the START signal, which used in the True-
Touch module during CSD mode. Refer to
Delta on page 89
When CSD_MODE is set to ‘0‘, it works on either the 32 kHz
clock or CPU clock, depending on the CLKSEL bit setting.
period
187.
). Refer to
pw
Operation
= COUNT VALUE
106. For a quick reference of all PSoC reg-
for more details on TrueTouch CSD mode.
Figure 19-2
and
decimal
Figure
* CLK
19-3.
period
11.1.1.5 Sigma
period
= TC
). The
pw
161
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