CY8CTMG200-16LGXIT Cypress Semiconductor Corp, CY8CTMG200-16LGXIT Datasheet - Page 58

• Manufacturer Part Number: CY8CTMG200-16LGXIT
• Description: IC MCU 32K FLASH 16-COL
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-16LGXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 13
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Interrupt High mode. If the last value read from the GPIO
was ‘1’, the GPIO is in Interrupt Low mode.
Table 6-1. GPIO Interrupt Modes
Figure 6-3
is set, and that the IOINT bit was set to high. The Change
Interrupt mode relies on the value of an internal read register
to determine if the pin state changed. Therefore, the port
that contains the GPIO in question must be read during
every interrupt service routine. If the port is not read, the
Interrupt mode acts as if it is in high mode when the latch
value is ‘0’ and low mode when the latch value is ‘1’.
Figure 6-3. GPIO Interrupt Mode IOINT = 1
General Purpose I/O (GPIO)
58
Interrupt Enable
Interrupt Enable
(c)
(a)
IE
0
0
1
1
GPIO Pin
GPIO Pin
Waveform
Set
Pin State
Set
Waveform
Pin State
Last Value Read From Pin was ‘0’
Last Value Read From Pin was ‘1’
assumes that the GIE is set, GPIO interrupt mask
IOINT
0
1
0
1
Interrupt
Bit interrupt disabled, INTO deasserted
Bit interrupt disabled, INTO d-asserted
Assert INTO when PIN = low
Assert INTO when PIN = change from last read
Interrupt
Occurs
Occurs
Interrupt Enable
Pin State Waveform
(b)
GPIO Pin
(d)
Waveform
Pin State
Enable Set
Description
Set
GPIO Pin
Interrupt
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Interrupt
Occurs
Interrupt
Occurs
6.1.7
GPIO pins are configured to either output data through CPU
writes to the PRTxDR registers or to bypass the port's data
register and output data from internal functions instead. The
bypass path is shown in
which is selected by the Alt Select input. These data bypass
options are selected in one of two ways.
■
■
For internal functions such as I2C and SPI, the hardwire
automatically selects the bypass mode for the required
pins when the function is enabled. In addition, some
bypass outputs are selected by the user through the
OUT_P1 register. For these, the pin is configured for
data bypass when the register bit is set high, which
allows an internal signal to be driven to the pin.
For all bypass modes, the wanted drive mode of the pin
must be configured separately for each pin, with the
PRTxDM1 and PRTxDM0 registers.
Data Bypass
Figure 6-1
by the Alt Data input,
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