CY8CTMG200-16LGXIT Cypress Semiconductor Corp, CY8CTMG200-16LGXIT Datasheet - Page 30

• Manufacturer Part Number: CY8CTMG200-16LGXIT
• Description: IC MCU 32K FLASH 16-COL
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-16LGXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 13
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.5
The M8C has a total of seven instruction formats that use
instruction lengths of one, two, and three bytes. All instruc-
tion bytes are taken from the program memory (Flash),
using an address and data bus that are independent from
the address and data buses used for register and RAM
access.
While examples of instructions are given in this section,
refer to the PSoC Designer Assembly Language User Guide
for detailed information on individual instructions.
2.5.1
Many instructions, such as some of the MOV instructions,
have single-byte forms because they do not use an address
or data as an operand. As shown in
instructions use an 8-bit opcode. The set of one-byte
instructions are divided into four categories, according to
where their results are stored.
Table 2-3. One-Byte Instruction Format
The first category of one-byte instructions are those that do
not update any registers or RAM. Only the one-byte NOP
and SSC instructions fit this category. While the program
counter is incremented as these instructions execute, they
do not cause any other internal M8C registers to update, nor
do these instructions directly affect the register space or the
RAM address space. The SSC instruction causes SROM
code to run, which modifies RAM and the M8C internal reg-
isters.
The second category contains the two PUSH instructions.
The PUSH instructions are unique because they are the only
one-byte instructions that modify a RAM address. These
instructions automatically increment the SP.
The third category contains the HALT instruction. The
instruction is unique because it is the only one-byte instruc-
tion that modifies a user register. The HALT instruction mod-
ifies user register space address FFh (CPU_SCR0 register).
The final category for one-byte instructions are those that
update the internal M8C registers. This category holds the
largest number of instructions:
MOV
instructions cause the A, X, and SP registers or SRAM to
update.
CPU Core (M8C)
30
8-Bit Opcode
,
POP
Byte 0
,
Instruction Formats
RET
One-Byte Instructions
,
RETI
,
RLC
,
ASL
ROMX
,
ASR
,
RRC
Table
,
CPL
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
,
2-3, one-byte
SWAP
,
DEC
. These
,
INC
HALT
,
2.5.2
The majority of M8C instructions are two bytes in length.
While these instructions are divided into categories identical
to the one-byte instructions, this does not provide a useful
distinction between the three two-byte instruction formats
that the M8C uses.
Table 2-4. Two-Byte Instruction Formats
The first two-byte instruction format, shown in the first row of
Table
JACC
uses only 4 bits for the instruction opcode, leaving 12 bits to
store the relative destination address in a two’s-complement
form. These instructions can change program execution to
an address relative to the current address by -2048 or
+2047.
The second two-byte instruction format, shown in the sec-
ond row of
Source Immediate addressing mode (see the PSoC
Designer Assembly Language User Guide). The destination
for these instructions is an internal M8C register, while the
source is a constant value. An example of this type of
instruction is
The third two-byte instruction format, shown in the third row
of
addressing modes. The following is a list of the addressing
modes that use this third two-byte instruction format:
■
■
■
■
■
■
For more information on addressing modes see the PSoC
Designer Assembly Language User Guide.
4-Bit Opcode 12-Bit Relative Address
8-Bit Opcode
8-Bit Opcode
Table
Source Direct (
Source Indexed (
Destination Direct (
Destination Indexed (
Source Indirect Post Increment (
Destination Indirect Post Increment (
2-4,
,
Byte 0
INDEX
2-4,
is used by short jumps and calls:
Table
ADD A, 7
Two-Byte Instructions
is used by a wide range of instructions and
,
JC
2-4,
ADD A, [7]
,
8-Bit Data
8-Bit Address
ADD A, [X+7]
JNC
is used by instructions that employ the
ADD [7], A
ADD [X+7], A
.
,
JNZ
Byte 1
,
JZ
)
. This instruction format
MVI A, [7]
)
)
MVI [7], A
)
CALL
)
,
JMP
)
,
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