CY8CTMG200-16LGXIT Cypress Semiconductor Corp, CY8CTMG200-16LGXIT Datasheet - Page 149

• Manufacturer Part Number: CY8CTMG200-16LGXIT
• Description: IC MCU 32K FLASH 16-COL
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-16LGXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 13
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Control Register
18.2.3
The SPI Control Register (SPI_CR) is the SPI’s control reg-
ister.
Bit 7: LSb First. This bit determines how the serial data is
shifted out, either LSb or MSb first.
Bit 6: Overrun. This status bit indicates whether or not
there was a receive buffer overrun. A read from the receive
buffer after each received byte must be performed before
the reception of the next byte in order to avoid an overrun
condition.
Bit 5: SPI Complete. This status bit indicates the comple-
tion of a transaction. A read from this register clears this bit.
18.2.3.1
Table 18-4. SPI Control Register Descriptions
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
0,2Bh
LEGEND
#
Address
Bit #
Access is bit specific. Refer to the register detail for additional information.
7
6
5
4
3
2
1
0
LSb First
Overrun
SPI Complete
TX Reg Empty
RX Reg Full
Clock Phase
Clock Polarity
Enable
SPI_CR
SPI_CR Register
SPI Control Register Definitions
Name
Name
LSb First
Bit 7
Read/Write
Read Only
Read Only
Read Only
Read Only
Read/Write
Read/Write
Read/Write
Overrun
Bit 6
Access
Complete
Bit 5
SPI
0 = Data shifted out MSb First.
1 = Data shifted out LSb First.
0 = No overrun.
1 = Indicates new byte received before previous one is read.
0 = Transaction in progress.
1 = Transaction is complete. Reading SPI_CR clears this bit.
0 = TX register is full.
1 = TX register is empty. Writing SPI_TXR register clears this bit.
0 = RX register is not full.
1 = RX register is full. Reading SPI_RXR register clears this bit.
0 = Data changes on trailing edge.
1 = Data changes on leading clock edge.
0 = Non-inverted, clock idles low (modes 0, 2).
1 = Inverted, clock idles high (modes 1, 3).
0 = Disable SPI function.
1 = Enable SPI function.
TX Reg
Empty
Bit 4
Bit 4: TX Reg Empty. This status bit indicates whether or
not the Transmit register is empty.
Bit 3: RX Reg Full. This status bit indicates a Receive reg-
ister full condition.
Bit 2: Clock Phase. This bit determines the edge (rising or
falling) on which the data changes.
Bit 1: Clock Polarity. This bit determines the logic level
the clock codes to in its idle state.
Bit 0: Enable. This bit enables the SPI block.
For additional information, refer to the
page
RX Reg Full
192.
Bit 3
Phase
Clock
Bit 2
Description
Polarity
Clock
Bit 1
SPI_CR register on
Enable
Bit 0
Access
# : 00
149
SPI
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