CY8CTMG200-16LGXIT Cypress Semiconductor Corp, CY8CTMG200-16LGXIT Datasheet - Page 179

• Manufacturer Part Number: CY8CTMG200-16LGXIT
• Description: IC MCU 32K FLASH 16-COL
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG200-16LGXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 13
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.3.12
The PSoC Memory Arbiter Data Register (PMAx_DR) is
used to read and write to a particular PMA channel by either
the USB SIE or the M8C. Note that a PMA channel may not
be used simultaneously by both the USB SIE and the M8C.
Bits 7 to 0: Data Byte[7:0]. When the M8C writes to this
register, the PMA registers the byte and then stores the
value at the address in SRAM indicated by the PMAx_WA
register.
After the value has been written to SRAM, the PMAx_WA
register is automatically incremented. When the USB SIE
writes to this register, the PMA registers the byte and then
stores the value in SRAM using the sum of the value of the
PMAx_WA register and the USB SIEs received byte count.
When the M8C reads this register, a pre-loaded value is
returned and the PMAx_RA value is automatically incre-
mented.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Address
0,58h
0,59h
0,5Ah
0,5Bh
0,5Ch
0,5Dh
0,5Eh
0,5Fh
0,64h
0,65h
0,66h
0,67h
0,68h
0,69h
0,6Ah
0,6Bh
PMA0_DR
PMA1_DR
PMA2_DR
PMA3_DR
PMA4_DR
PMA5_DR
PMA6_DR
PMA7_DR
PMA8_DR
PMA9_DR
PMA10_DR
PMA11_DR
PMA12_DR
PMA13_DR
PMA14_DR
PMA15_DR
PMAx_DR Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Data Byte[7:0]
Data Byte[7:0]
Data Byte[7:0]
Data Byte[7:0]
Data Byte[7:0]
Data Byte[7:0]
Data Byte[7:0]
Data Byte[7:0]
Data Byte[7:0]
Data Byte[7:0]
Data Byte[7:0]
Data Byte[7:0]
Data Byte[7:0]
Data Byte[7:0]
Data Byte[7:0]
Data Byte[7:0]
The new PMAx_RA value is used to fetch the next value
from the SRAM, to be ready for the next read from the chan-
nel's PMAx_DR register. When the USB SIE reads the
PMAx_DR register, it also receives a pre-loaded value,
which triggers the PMA logic to fetch the next value in
SRAM to be ready for the USB SIEs next read request. In all
read cases, the initial pre-load of the first address of the
channel is triggered by writing the first address of the chan-
nel to the channel's PMAx_RA register. Therefore, the
PMAx_RA register must be written after data has been
stored for the channel.
For additional information, refer to the
page
203.
Bit 3
Bit 2
Bit 1
PMAx_DR register on
Bit 0
Full-Speed USB
Access
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
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