LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 78

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

B. The IIR receive data available indication also occurs when the FIFO trigger level is reached. It is
C. The receiver line status interrupt (IIR=06H), has higher priority than the received data available
D. The data ready bit (LSR bit 0) is set as soon as a character is transferred from the shift register to the
When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts occur as follows:
A. A FIFO timeout interrupt occurs if all the following conditions exist:
At least one character is in the FIFO.
The most recent serial character received was longer than 4 continuous character times ago. (If 2 stop bits
are programmed, the second one is included in this time delay).
The most recent CPU read of the FIFO was longer than 4 continuous character times ago.
This will cause a maximum character received to interrupt issued delay of 160 msec at 300 BAUD with a
12 bit character.
B. Character times are calculated by using the RCLK input for a clock signal (this makes the delay
C. When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one
D. When a timeout interrupt has not occurred the timeout timer is reset after a new character is received
When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = "1", IER bit 1 = "1"), XMIT
interrupts occur as follows:
A. The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as
B. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time
Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received
data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register
empty interrupt.
FIFO Polled Mode Opertion
With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of
operation. Since the RCVR and XMITTER are controlled separately, either one or both can be in the
polled mode of operation. In this mode, the user's program will check RCVR and XMITTER status via the
LSR. LSR definitions for the FIFO Polled Mode are as follows:
Bit 0=1 as long as there is one byte in the RCVR FIFO.
Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as
when in the interrupt mode, the IIR is not affected since EIR bit 2=0.
Bit 5 indicates when the XMIT FIFO is empty.
Bit 6 indicates that both the XMIT FIFO and shift register are empty.
level; it is cleared as soon as the FIFO drops below its programmed trigger level.
cleared when the FIFO drops below the trigger level.
(IIR=04H) interrupt.
RCVR FIFO. It is reset when the FIFO is empty.
proportional to the baudrate).
character from the RCVR FIFO.
or after the CPU reads the RCVR FIFO.
soon as the transmitter holding register is written to (1 of 16 characters may be written to the XMIT
FIFO while servicing this interrupt) or the IIR is read.
whenever the following occurs: THRE=1 and there have not been at least two bytes at the same time
in the transmitter FIFO since the last THRE=1. The transmitter interrupt after changing FCR0 will be
immediate, if it is enabled.
78