LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 150

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LPC47N227TQFP

Manufacturer Part Number
LPC47N227TQFP
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of LPC47N227TQFP

Lead Free Status / RoHS Status
Not Compliant

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CR0D
CR0D can only be accessed in the configuration state and after the CSR has been initialized to 0DH.
This register is read only. CR0D contains the LPC47N227 Device ID. The default value of this register
after power up is 5AH on VCC POR.
CR0E
CR0E can only be accessed in the configuration state and after the CSR has been initialized to 0EH.
This register is read only. CR0E contains the current LPC47N227 Chip Revision Level starting at 00H.
CR0F
CR0F can only be accessed in the configuration state and after the CSR has been initialized to 0FH.
CR0F is a test control register and all bits must be treated as Reserved. Note: all test modes are
reserved for SMSC use. Activating test mode registers may produce undesired results.
BIT NO.
BIT NO.
7
0
1
2
3
4
5
6
7
UART 2 Speed
Type: R/W
BIT NAME
Type: R/W
BIT NAME
Test 0
Test 1
Test 2
Test 3
Test 4
Test 5
Test 6
Test 7
This bit enables the high speed mode of UART 2.
1 = High speed enabled
0 = Standard (default)
Table 70 – CR0F
UART Mode
Test 1
150
Default: 0x02 on VCC POR and HARD RESET
RESERVED FOR SMSC USE
DESCRIPTION
DESCRIPTION
Default: 0x00 on VCC POR

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