LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 128

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

The LPC47N227 offers support for Power Management Events (PMEs), also referred to as System
Control Interrupt (SCI) events in an ACPI system. A power management event is indicated to the
chipset via the assertion of the nIO_PME signal. In the LPC47N227, the nIO_PME is asserted by
active transitions on the ring indicator inputs nRI1 and nRI2, and programmable edges on GPIO pins.
The nIO_PME pin can be programmed to be active high or active low via bit 5 in the GPIO Polarity
Register 2 (CR34). The nIO_PME pin function defaults to active low, open-drain output. The output
buffer type of the pin can be programmed to be open-drain or push-pull via bit 7 in the GPIO Output
Type Register (CR39). This pin is powered by VTR. See the Configuration section for description on
these registers.
PME functionality is controlled by the PME status and enable registers in the runtime registers block,
which is located at the address programmed in register 0x30 in the Configuration section. The PME
Enable bit, PME_EN, globally controls PME Wake-up events.
nIO_PME signal can not be asserted. When PME_EN is asserted, any wake source whose individual
PME Wake Enable register bit is asserted can cause nIO_PME to become asserted.
The PME Status register indicates that an enabled wake source has occurred and if the PME_EN bit is
set, asserted the nIO_PME signal. The PME Status bit is asserted by active transitions of PME wake
sources. PME_STS will become asserted independent of the state of the global PME enable, PME_EN.
The following pertains to the PME status bits for each event:
!"
!"
For the GPIO events, the polarity of the edge used to set the status bit and generate a PME is
controlled by the GPIO Polarity Registers in the Configuration section.
(default) the status bit is set on the low-to-high edge. Status bits are cleared on a write of ‘1’.
In the LPC47N227 the nIO_PME pin can be programmed to be an open drain, active low, driver. The
LPC47N227 nIO_PME pin is fully isolated from other external devices that might pull the nIO_PME
signal low; i.e., the nIO_PME signal is capable of being driven high externally by another active device
or pullup even when the LPC47N227 VCC is grounded, providing VTR power is active.
PME Registers
The PME registers are run-time registers as follows. These registers are located in system I/O space
at an offset from Runtime Registers Block, the address programmed at register 0x30 in the
Configuration section.
The following registers are for GPIO PME events:
!" PME Wake Status 1 (PME_STS1), PME Wake Enable 1 (PME_EN1)
!" PME Wake Status 2 (PME_STS2), PME Wake Enable 2 (PME_EN2)
!" PME Wake Status 3 (PME_STS3), PME Wake Enable 3 (PME_EN3)
See PME register description in the Runtime Registers Section.
The output of the status bit for each event is combined with the corresponding enable bit to set the
PME status bit.
The status bit for any pending events must be cleared in order to clear the PME_STS bit. Status
bits are cleared on a write of ‘1’.
PME SUPPORT
128
When PME_EN is inactive, the
For non-inverted polarity