LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 169

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

Serial Port 1
Serial Port 2
Logical Device Base I/O Address and Range
LOGICAL
DEVICE
Parallel
FDC
Port
REGISTER
(FIR/CIR)
Table 110 – I/O Base Address Configuration Register Description
INDEX
0x2B
0x20
0x23
0x24
0x25
EPP is only available when
the base address is on an
(all modes supported,
on 8-byte boundaries
on 4-byte boundaries
on 8-byte boundaries
on 8 byte boundaries
on 8-byte boundaries
on 8-byte boundaries
(EPP Not supported)
[0x0100:0x03FC]
8-byte boundary)
[0x0100:0x03F8]
[0x0100:0x03F8]
[0x0100:0x03F8]
[0x0100:0x03F8]
[0x100:0x07F8]
BASE I/O
(Note 1)
RANGE
or
169
+0 : SRA
+1 : SRB
+2 : DOR
+3 : TDR
+4 : MSR/DSR
+5 : FIFO
+7 : DIR/CCR
+0 : Data/ecpAfifo
+1 : Status
+2 : Control
+400h : cfifo/ecpDfifo/tfifo/cnfgA
+401h : cnfgB
+402h : ecr
+3 : EPP Address
+4 : EPP Data 0
+5 : EPP Data 1
+6 : EPP Data 2
+7 : EPP Data 3
+0 : RB/TB/LSB div
+1 : IER/MSB div
+2 : IIR/FCR
+3 : LCR
+4 : MCR
+5 : LSR
+6 : MSR
+7 : SCR
+0 : RB/TB/LSB div
+1 : IER/MSB div
+2 : IIR/FCR
+3 : LCR
+4 : MCR
+5 : LSR
+6 : MSR
+7 : SCR
+0 : DR/SCEA/CIRC/IDH/(IRDACR/BOFH)
+1 : INTID/SCEB/CIRCR/IDL/BOFL
+2 : IER/FIFOT/CIRBR/CID/BWCL
+3 : LSR/LSA/VERN/(BWCH/TDSH)
+4 : LCA/(IRQL/DMAC)/TDSL
+5 : LCB/RDSH
+6 : BS/RDSL
+7 : MCR
BASE OFFSETS
FIXED