LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 156

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

CR21
CR21 can only be accessed in the configuration state and after the CSR has been initialized to 21H.
CR21 is the Floppy on Parallel Port Pin register.
CR22
The ECP Software Select register CR22 contains the ECP IRQ Select bits and the ECP DMA Select
bits. CR22 is part of the ECP DMA/IRQ Software Indicators described in the ECP cnfgB register.
BIT NO.
BIT NO.
3-7
0,1
0
1
2
3
4
5
6
7
2
TIMEOUT_SELECT
Type: R/W
Type: R/W
BIT NAME
BIT NAME
Reserved
Reserved
Reserved
FDC_PP
ADR4
ADR5
ADR6
ADR7
ADR8
ADR9
FDC on PP/EPP Timeout Select
Read Only. A read returns 0.
Read Only. A read returns 0.
FDC Base Address bits for decoder.
FDC on Parallel Port Pin
This bit selects the means of clearing the TIMEOUT bit in the
EPP Status register. If the TIMEOUT_SELECT bit is cleared (‘0’),
the TIMEOUT bit is cleared on the trailing edge of the read of the
EPP Status Register (default).
If the TIMEOUT_SELECT bit is set (‘1’), the TIMEOUT bit is
cleared on a write of ‘1’ to the TIMEOUT bit.
Read Only. A read returns 0.
BIT1
0
0
1
1
FDC Base Address
Table 80 – CR20
Table 81 – CR21
BIT0
156
0
1
0
1
Bits in PP mode Register control the FDC
on the parallel port, the FDC_PP pin
function is not used.
The FDC_PP pin controls the FDC on the
PP as follows: (non-inverted polarity) when
the pin is low, the parallel port pins are used
for a floppy disk controller: drive 0 is on
FDC pins, drive 1 is on parallel port pins.
The FDC_PP pin controls the FDC on the
PP as follows: (non-inverted polarity) when
the pin is low, the parallel port pins are used
for a floppy disk controller: drive 0 is on
parallel port pins and drive 1 is on parallel
port pins.
Reserved
DESCRIPTION
DESCRIPTION
Default: 0x3C on VCC POR
Default: 0x00 on VCC POR
DESCRIPTION