LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 101

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

ADDRESS OFFSET = 400H
Mode = 111
This register is a read only register. When read, 10H is returned. This indicates to the system that this is
an 8-bit implementation. (PWord = 1 byte)
cnfgB (Configuration Register B)
ADDRESS OFFSET = 401H
Mode = 111
BIT 7 compress
This bit is read only. During a read it is a low level. This means that this chip does not support hardware
RLE compression. It does support hardware de-compression!
BIT 6 intrValue
Returns the value of the interrupt to determine possible conflicts.
BITS [5:3] Parallel Port IRQ (read-only)
Refer to Table 40B.
BITS [2:0] Parallel Port DMA (read-only)
Refer to Table 40C.
ecr (Extended Control Register)
ADDRESS OFFSET = 402H
Mode = all
This register controls the extended ECP parallel port functions.
BITS 7,6,5
These bits are Read/Write and select the Mode.
BIT 4 nErrIntrEn
Read/Write (Valid only in ECP Mode)
1:
0:
BIT 3 dmaEn
Read/Write
1:
0:
BIT 2 serviceIntr
Read/Write
1:
0:
case dmaEn=1:
Disables the interrupt generated on the asserting edge of nFault.
Enables an interrupt pulse on the high to low edge of nFault. Note that an interrupt will be generated if
nFault is asserted (interrupting) and this bit is written from a 1 to a 0. This prevents interrupts from
being lost in the time between the read of the ecr and the write of the ecr.
Enables DMA (DMA starts when serviceIntr is 0).
Disables DMA unconditionally.
Disables DMA and all of the service interrupts.
Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has occurred
serviceIntr bit shall be set to a 1 by hardware. It must be reset to 0 to re-enable the interrupts. Writing
this bit to a 1 will not cause an interrupt.
During DMA (this bit is set to a 1 when terminal count is reached).
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