LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 71

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

Bit 0
This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt
is pending. When bit 0 is a logic "0", an interrupt is pending and the contents of the IIR may be used as a
pointer to the appropriate internal service routine. When bit 0 is a logic "1", no interrupt is pending.
Bits 1 and 2
These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the
Interrupt Control Table.
Bit 3
In non-FIFO mode, this bit is a logic "0". In FIFO mode this bit is set along with bit 2 when a timeout
interrupt is pending.
Bits 4 and 5
These bits of the IIR are always logic "0".
Bits 6 and 7
These two bits are set when the FIFO CONTROL Register bit 0 equals 1.
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