LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 20

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

SYNC Timeout
The SYNC value is driven within 3 clocks. If the
host observes 3 consecutive clocks without a
valid SYNC pattern, it will abort the cycle.
The LPC47N227 does not assume any particular
timeout. When the host is driving SYNC, it may
have to insert a very large number of wait states,
depending on PCI latencies and retries.
SYNC Patterns and Maximum Number of
SYNCS
If the SYNC pattern is 0101, then the host
assumes that the maximum number of SYNCs is
8.
If the SYNC pattern is 0110, then no maximum
number of SYNCs is assumed. The LPC47N227
has protection mechanisms to complete the
cycle. This is used for EPP data transfers and
will utilize the same timeout protection that is in
EPP.
SYNC Error Indication
The LPC47N227 reports errors via the LAD[3:0]
= 1010 SYNC encoding.
If
LPC47N227, data will still be transferred in the
next two nibbles. This data may be invalid, but it
will be transferred by the LPC47N227.
host was writing data to the LPC47N227, the
data had already been transferred.
In the case of multiple byte cycles, such as DMA
cycles, an error SYNC terminates the cycle.
Therefore, if the host is transferring 4 bytes from
a device, if the device returns the error SYNC in
the first byte, the other three bytes will not be
transferred.
the
host
was
reading
data
from
If the
the
20
I/O and DMA START Fields
I/O and DMA cycles use a START field of 0000.
Reset Policy
The following rules govern the reset policy:
1)
2)
LPC Transfers
Wait State Requirements
I/O Transfers
The LPC47N227 inserts three wait states for an
I/O read and two wait states for an I/O write
cycle.
transfers. The exception to this is for transfers
where IOCHRDY would be deasserted in an ISA
transfer (i.e., EPP or IrCC transfers) in which
case the sync pattern of 0110 is used and a
large number of syncs may be inserted (up to
330 which corresponds to a timeout of 10us).
DMA Transfers
The LPC47N227 inserts three wait states for a
DMA read and four wait states for a DMA write
cycle.
transfers.
See the example timing for the LPC cycles in the
“Timing Diagrams” section.
When nPCI_RESET goes inactive (high),
the clock is assumed to have been running
for 100usec prior to the removal of the reset
signal, so that everything is stable. This is
the same reset active time after clock is
stable that is used for the PCI bus.
When nPCI_RESET goes active (low):
a)
b)
A SYNC of 0101 is used for all DMA
A SYNC of 0110 is used for all I/O
The host drives the nLFRAME signal
high, tristates the LAD[3:0] signals, and
ignores the nLDRQ signal.
The LPC47N227 ignores nLFRAME, tri-
states the LAD[3:0] pins and drives the
nLDRQ signal inactive (high).