LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 117

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

EOI/ISR Read Latency
Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency
could cause an EOI or ISR Read to precede an IRQ transition that it should have followed. This could
cause a system fault. The host interrupt controller is responsible for ensuring that these latency issues
are mitigated. The recommended solution is to delay EOIs and ISR Reads to the interrupt controller by
the same amount as the SER_IRQ Cycle latency in order to ensure that these events do not occur out
of order.
AC/DC Specification Issue
All SER_IRQ agents must drive / sample SER_IRQ synchronously related to the rising edge of PCI bus
clock. The SER_IRQ pin uses the electrical specification of PCI bus. Electrical parameters will follow
PCI spec. section 4, sustained tri-state.
Reset and Initialization
The SER_IRQ bus uses nPCI_RESET as its reset signal. The SER_IRQ pin is tri-stated by all agents
while nPCI_RESET is active. With reset, SER_IRQ Slaves are put into the (continuous) IDLE mode.
The Host Controller is responsible for starting the initial SER_IRQ Cycle to collect system’s IRQ/Data
default values. The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse
width) for subsequent SER_IRQ Cycles. It is Host Controller’s responsibility to provide the default
values to 8259’s and other system logic before the first SER_IRQ Cycle is performed. For SER_IRQ
system suspend, insertion, or removal application, the Host controller should be programmed into
Continuous (IDLE) mode first. This is to guarantee SER_IRQ bus is in IDLE state before the system
configuration changes.
Routable IRQ Inputs
The routable IRQ input (IRQINx) functions are on pins 51 (IRQIN1) and 52 (IRQIN2), muxed onto GP13
and GP14 respectively as inputs. The IRQINx pin’s IRQ time slot in the Serial IRQ stream is selected
via a 4-bit control register for each IRQIN function (CR29 for IRQIN1, CR2A for IRQIN2). A value of
0000 disables the IRQ function.
The part is able to generate a PME and an SMI from both of the IRQ inputs through the GPIO bits in
the PME and SMI status and enable registers. The edge is programmable through the polarity bit of
the GPIO control register.
User Note: In order to use an IRQ for one of the IRQINx inputs that are muxed on the GPIO pins, the
corresponding IRQ must not be used for any of the devices in the LPC47N227. Otherwise contention
may occur.
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