LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 130

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

NAME/DEFAULT
PME_STS
Default = 0x00
on VTR POR
PME_EN
Default = 0x00
on VTR POR
PME_STS1
Default = 0x00
on VTR POR
REGISTER
Table 53 – Runtime Registers Block Description
OFFSET
(R/W)
(R/W)
(R/W)
00
01
02
Bit[0] PME_Status
= 0 (default)
= 1 Set when LPC47N227 would normally assert the
Bit[7:1] Reserved
PME_Status is not affected by Vcc POR, SOFT RESET
or HARD RESET.
Writing a “1” to PME_Status will clear it and cause the
LPC47N227 to stop asserting nIO_PME, if enabled.
Writing a “0” to PME_Status has no effect.
Bit[0] PME_En
= 0
= 1
Bit[7:1] Reserved
PME_En is not affected by Vcc POR, SOFT RESET or
HARD RESET
PME Wake Status Register 1
This register indicates the state of the individual PME
wake sources, independent of the individual source
enables or the PME_En bit.
If the wake source has asserted a wake event, the
associated PME Wake Status bit will be a “1”.
Bit[0] GP10
Bit[1] GP11
Bit[2] GP12
Bit[3] GP13
Bit[4] GP14
Bit[5] GP15
Bit[6] GP16
Bit[7] GP17
The PME Wake Status register is not affected by Vcc
POR, SOFT RESET or HARD RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any
bit in PME Wake Status Register has no effect.
nIO_PME signal, independent of the state of the
PME_En bit. Set when a bit in a PME Wake
Status register and its associated enable bit set.
130
nIO_PME signal assertion is disabled (default)
Enables LPC47N227 to assert nIO_PMEsignal
DESCRIPTION