LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 31

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

Digital Input Register (DIR)
Address 3F7 READ ONLY
This register is read-only in all modes.
PC-AT Mode
BIT 0 - 6 UNDEFINED
The data bus outputs D0 - 6 are read as ‘0’.
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the
value programmed in the Force FDD Status Change Register (CR17). See the Configuration section for
register description.
PS/2 Mode
BIT 0 nHIGH DENS
This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and
300 Kbps are selected.
BITS 1 - 2 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the
individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250
Kbps after a hardware reset.
BITS 3 - 6 UNDEFINED
Always read as a logic "1"
RESET
RESET
COND.
COND.
FIFO THRESHOLD
CHG
DSK
CHG
N/A
DSK
N/A
7
EXAMPLES
7
15 bytes
2 bytes
8 bytes
1 byte
N/A
N/A
6
1
6
0
N/A
N/A
5
1
5
0
1 x 16 #s - 1.5 #s = 14.5 #s
2 x 16 #s - 1.5 #s = 30.5 #s
8 x 16 #s - 1.5 #s = 126.5 #s
15 x 16 #s - 1.5 #s = 238.5 #s
MAXIMUM DELAY TO SERVICING AT
N/A
31
N/A
4
1
4
0
500 Kbps DATA RATE
N/A
N/A
3
1
3
0
DRATE
SEL1
N/A
N/A
2
2
0
DRATE
SEL0
N/A
N/A
1
1
0
nDENS
nHIGH
N/A
0
1
0
0