LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 143

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

CR03 can only be accessed in the configuration state and after the CSR has been initialized to 03H.
NOTE
BIT NO.
1
2,3
: See NOTE
0
1
4
5
6
7
Type: R/W
Reserved
Enhanced Floppy
Mode 2
Reserved
DRVDEN1
MFM
IDENT
Reserved
2
BIT NAME
in section CR05.
Read Only. A read returns 0.
Read Only. A read returns 0.
Bit 4
IDENT is used in conjunction with MFM to define the FDC interface
mode.
Read Only. A read returns 0.
0
1
IDENT
Bit 1
FDC Miscellaneous
0
1
1
1
0
0
Table 59 - CR03
Pin DRVDEN1 Output
Output Programmed DRVDEN1 Value
Force DRVDEN1 Output High (default)
143
Floppy Mode – Refer to the description of the TAPE
DRIVE REGISTER (TDR) for more information on
these modes.
NORMAL Floppy Mode (Default)
Enhanced Floppy Mode 2 (OS2)
MFM
1
0
1
0
Default: 0x70 on VCC POR
DESCRIPTION
MODE
AT Mode (Default)
Reserved
PS/2
Model 30
1