LPC47N227TQFP Standard Microsystems (SMSC), LPC47N227TQFP Datasheet - Page 149

• Manufacturer Part Number: LPC47N227TQFP
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47N227TQFP

• Lead Free Status / RoHS Status: Not Compliant

CR0C
CR0C can only be accessed in the configuration state and after the CSR has been initialized to 0CH.
CR0C controls the operating mode of the UART. This register is reset to the default state by a POR or
a hardware reset.
BIT NO.
BIT NO.
3, 4, 5
0
1
2
3
4
5
6
7
0
1
2
6
DRT1
0
0
1
1
UART 2 Duplex
UART 2 MODE
UART 1 Speed
UART 2 XMIT
UART 2 RCV
FDD0 DTR0
FDD0 DTR1
FDD1 DTR0
FDD1 DTR1
FDD2 DTR0
FDD3 DTR0
FDD3 DTR1
FDD2 DTR1
Type: R/W
Type: R/W
BIT NAME
BIT NAME
Polarity
Polarity
DRT0
0
1
0
1
Table 68 – Drive Rate Table (Recommended)
360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format
3-Mode Drive
2 Meg Tape
Reserved
Floppy Disk Drive 0 Drive Rate Table Bit 0.
Floppy Disk Drive 0 Drive Rate Table Bit 1.
Floppy Disk Drive 1 Drive Rate Table Bit 0.
Floppy Disk Drive 1 Drive Rate Table Bit 1.
Floppy Disk Drive 2 Drive Rate Table Bit 0.
Floppy Disk Drive 2 Drive Rate Table Bit 1.
Floppy Disk Drive 3 Drive Rate Table Bit 0.
Floppy Disk Drive 3 Drive Rate Table Bit 1.
0 = RX input active high (default).
1 = RX input active low.
0 = TX output active high.
1 = TX output active low (default).
This bit is used to define the FULL/HALF DUPLEX operation of
UART 2.
1 = Half duplex
0 = Full duplex (default)
UART 2 Mode
5 4 3
0 0 0
0 0 1
0 1 0
0 1 1
1 x x
This bit enables the high speed mode of UART 1.
1 = High speed enabled
0 = Standard (default)
Table 67 – CR0B
Table 69 – CR0C
Standard COM Functionality (default)
IrDA (HPSIR)
Amplitude Shift Keyed IR
Reserved
Reserved
UART Mode
Drive Rate
149
Default: 0x02 on VCC POR and HARD RESET
FORMAT
DESCRIPTION
DESCRIPTION
Default: 0x00 on VCC POR