D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 87

IC H8/3002 ROMLESS 100QFP

D13002F16V

Manufacturer Part Number
D13002F16V
Description
IC H8/3002 ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of D13002F16V

Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D13002F16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
4.3 Interrupts
Interrupt exception handling can be requested by seven external sources (NMI, IRQ
30 internal sources in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources
and indicates the number of interrupts of each type.
The on-chip supporting modules that can request interrupts are the watchdog timer (WDT),
refresh controller, 16-bit integrated timer-pulse unit (ITU), DMA controller (DMAC), serial
communication interface (SCI), and A/D converter. Each interrupt source has a separate vector
address.
NMI is the highest-priority interrupt and is always accepted. Interrupts are controlled by the
interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority
levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt
priority registers A and B (IPRA and IPRB) in the interrupt controller.
For details on interrupts see section 5, Interrupt Controller.
Notes: Numbers in parentheses are the number of interrupt sources.
1.
2.
Interrupts
When the watchdog timer is used as an interval timer, it generates an interrupt
request at every counter overflow.
When the refresh controller is used as an interval timer, it generates an interrupt
request at compare match.
Figure 4-4 Interrupt Sources and Number of Interrupts
External interrupts
Internal interrupts
70
NMI (1)
IRQ to IRQ (6)
WDT
Refresh controller
ITU (15)
DMAC (4)
SCI (8)
A/D converter (1)
0
*1
(1)
5
*2
(1)
0
to IRQ
5
) and

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