D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 438

• Manufacturer Part Number: D13002F16V
• Description: IC H8/3002 ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13002F16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13.1.3 Input/Output Pins
The SCI has serial pins for each channel as listed in table 13-1.
Table 13-1 SCI Pins
Channel
0
1
13.1.4 Register Configuration
The SCI has internal registers as listed in table 13-2. These registers select asynchronous or
synchronous mode, specify the data format and bit rate, and control the transmitter and receiver
sections.
Table 13-2 Registers
Channel
0
1
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, to clear flags.
Name
Serial clock pin
Receive data pin
Transmit data pin
Serial clock pin
Receive data pin
Transmit data pin
Address
H'FFB0
H'FFB1
H'FFB2
H'FFB3
H'FFB4
H'FFB5
H'FFB8
H'FFB9
H'FFBA
H'FFBB
H'FFBC
H'FFBD
*1
Name
Serial mode register
Bit rate register
Serial control register
Transmit data register
Serial status register
Receive data register
Serial mode register
Bit rate register
Serial control register
Transmit data register
Serial status register
Receive data register
Abbreviation
SCK
RxD
TxD
SCK
RxD
TxD
0
1
0
1
0
1
422
I/O
Input/output
Input
Output
Input/output
Input
Output
Abbreviation
SMR
BRR
SCR
TDR
SSR
RDR
SMR
BRR
SCR
TDR
SSR
RDR
Function
SCI
SCI
SCI
SCI
SCI
SCI
R/W
R/W
R/W
R/W
R/W
R/(W)
R
R/W
R/W
R/W
R/W
R/(W)
R
0
0
0
1
1
1
clock input/output
receive data input
transmit data output
clock input/output
receive data input
transmit data output
*2
*2
Initial Value
H'00
H'FF
H'00
H'FF
H'84
H'00
H'00
H'FF
H'00
H'FF
H'84
H'00