D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 323

IC H8/3002 ROMLESS 100QFP

D13002F16V

Manufacturer Part Number
D13002F16V
Description
IC H8/3002 ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of D13002F16V

Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
SCI
Peripherals
DMA, PWM, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D13002F16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture
function for GRA and GRB, and specifies the functions of the TIOCA and TIOCB pins. If the
output compare function is selected, TIOR also selects the type of output. If input capture is
selected, TIOR also selects the edge or edges of the input capture signal.
TIOR is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bits 6 to 4—I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function.
Bit 6
IOB2
0
1
Notes: 1. After a reset, the output is 0 until the first compare match.
Bit
Initial value
Read/Write
2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output
Bit 5
IOB1
0
1
0
1
instead.
Reserved bit
Bit 4
IOB0
0
1
0
1
0
1
0
1
7
1
I/O control B2 to B0
These bits select GRB functions
IOB2
R/W
Function
GRB is an output
compare register
GRB is an input
capture register
6
0
IOB1
R/W
5
0
307
IOB0
R/W
4
0
No output at compare match
0 output at GRB compare match
1 output at GRB compare match
Output toggles at GRB compare match
(1 output in channel 2)
GRB captures rising edge of input
GRB captures falling edge of input
GRB captures both edges of input
Reserved bit
3
1
IOA2
R/W
I/O control A2 to A0
These bits select GRA
functions
2
0
*1, *2
IOA1
R/W
1
0
*1
*1
(Initial value)
IOA0
R/W
0
0

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