D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 254

• Manufacturer Part Number: D13002F16V
• Description: IC H8/3002 ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13002F16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.6.7 Memory and I/O Address Register Values
Table 8-14 indicates the address ranges that can be specified in the memory and I/O address
registers (MAR and IOAR).
Table 8-14 Address Ranges Specifiable in MAR and IOAR
MAR
IOAR
Note: MAR bits 23 to 20 are ignored in 1-Mbyte mode.
8.6.8 Bus Cycle when Transfer is Aborted
When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME
bit, if this halts a channel for which the DMAC has a transfer request pending internally, a dead
cycle may occur. This dead cycle does not update the halted channel’s address register or counter
value. Figure 8-27 shows an example in which an auto-requested transfer in cycle-steal mode on
channel 0 is aborted by clearing the DTE bit in channel 0.
ø
Address bus
RD
HWR, LWR
Figure 8-27 Bus Timing at Abort of DMA Transfer in Cycle-Steal Mode
1-Mbyte Mode
H'00000 to H'FFFFF
(0 to 1048575)
H'FFF00 to H'FFFFF
(1048320 to 1048575)
CPU cycle
T
1
T
2
T
d
T
1
DMAC cycle
T
2
16-Mbyte Mode
H'000000 to H'FFFFFF
(0 to 16777215)
H'FFFF00 to H'FFFFFF
(16776960 to 16777215)
T
1
238
T
2
T
1
CPU cycle
DTE bit is
cleared
T
2
T
3
T
d
DMAC
cycle
T
d
T
1
CPU cycle
T
2