D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 15

• Manufacturer Part Number: D13002F16V
• Description: IC H8/3002 ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13002F16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 14
14.1
14.2
14.3
14.4
14.5
14.6
Section 15
15.1
15.2
15.3
Section 16
16.1
16.2
16.3
16.4
Section 17
17.1
17.2
Overview ........................................................................................................................ 479
14.1.1
14.1.2
14.1.3
14.1.4
Register Descriptions...................................................................................................... 483
14.2.1
14.2.2
14.2.3
CPU Interface ................................................................................................................. 488
Operation ........................................................................................................................ 489
14.4.1
14.4.2
14.4.3
14.4.4
Interrupts ........................................................................................................................ 495
Usage Notes .................................................................................................................... 495
Overview ........................................................................................................................ 501
15.1.1
15.1.2
System Control Register (SYSCR)................................................................................. 502
Operation ........................................................................................................................ 503
Overview ........................................................................................................................ 505
16.1.1
Oscillator Circuit ............................................................................................................ 506
16.2.1
16.2.2
Duty Adjustment Circuit................................................................................................. 511
Prescalers ........................................................................................................................ 511
Overview ........................................................................................................................ 513
Register Configuration.................................................................................................... 514
17.2.1
A/D Converter
Features........................................................................................................... 479
Block Diagram................................................................................................ 480
Input Pins ........................................................................................................ 481
Register Configuration.................................................................................... 482
A/D Data Registers A to D (ADDRA to ADDRD)........................................ 483
A/D Control/Status Register (ADCSR) .......................................................... 484
A/D Control Register (ADCR) ....................................................................... 487
Single Mode (SCAN = 0) ............................................................................... 489
Scan Mode (SCAN = 1).................................................................................. 491
Input Sampling and A/D Conversion Time .................................................... 493
External Trigger Input Timing........................................................................ 494
RAM
Block Diagram................................................................................................ 501
Register Configuration.................................................................................... 502
Clock Pulse Generator
Block Diagram................................................................................................ 505
Connecting a Crystal Resonator ..................................................................... 506
External Clock Input....................................................................................... 508
Power-Down State
System Control Register (SYSCR)................................................................. 514
............................................................................................................. 501
............................................................................................ 479
.................................................................................... 513
............................................................................. 505