D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 13

• Manufacturer Part Number: D13002F16V
• Description: IC H8/3002 ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13002F16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10.4
10.5
10.6
Section 11
11.1
11.2
11.3
11.4
Operation ........................................................................................................................ 317
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
10.4.7
10.4.8
10.4.9
Interrupts ........................................................................................................................ 358
10.5.1
10.5.2
10.5.3
Usage Notes .................................................................................................................... 362
Overview ........................................................................................................................ 377
11.1.1
11.1.2
11.1.3
11.1.4
Register Descriptions...................................................................................................... 381
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.2.7
11.2.8
11.2.9
11.2.10 TPC Output Mode Register (TPMR).............................................................. 392
Operation ........................................................................................................................ 394
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
Usage Notes .................................................................................................................... 401
11.4.1
11.4.2
Overview......................................................................................................... 317
Basic Functions............................................................................................... 318
Synchronization .............................................................................................. 328
PWM Mode .................................................................................................... 330
Reset-Synchronized PWM Mode ................................................................... 334
Complementary PWM Mode.......................................................................... 337
Phase Counting Mode..................................................................................... 347
Buffering......................................................................................................... 349
ITU Output Timing......................................................................................... 356
Setting of Status Flags .................................................................................... 358
Clearing of Status Flags.................................................................................. 360
Interrupt Sources and DMA Controller Activation ........................................ 361
Programmable Timing Pattern Controller
Features........................................................................................................... 377
Block Diagram................................................................................................ 378
TPC Pins ......................................................................................................... 379
Registers ......................................................................................................... 380
Port A Data Direction Register (PADDR) ...................................................... 381
Port A Data Register (PADR) ......................................................................... 381
Port B Data Direction Register (PBDDR) ...................................................... 382
Port B Data Register (PBDR) ......................................................................... 382
Next Data Register A (NDRA)....................................................................... 383
Next Data Register B (NDRB) ....................................................................... 385
Next Data Enable Register A (NDERA) ........................................................ 387
Next Data Enable Register B (NDERB)......................................................... 388
TPC Output Control Register (TPCR)............................................................ 389
Overview......................................................................................................... 394
Output Timing................................................................................................. 395
Normal TPC Output........................................................................................ 396
Non-Overlapping TPC Output........................................................................ 398
TPC Output Triggering by Input Capture....................................................... 400
Operation of TPC Output Pins........................................................................ 401
Note on Non-Overlapping Output .................................................................. 401
......................................... 377