D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 448

• Manufacturer Part Number: D13002F16V
• Description: IC H8/3002 ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13002F16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if TDR does not contain new transmit data when the MSB is transmitted.
Bit 2
TEIE
0
1
Note: * TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in SSR,
Bits 1 and 0—Clock Enable 1 and 0 (CKE1/0): These bits select the SCI clock source and
enable or disable clock output from the SCK pin. Depending on the settings of CKE1 and CKE0,
the SCK pin can be used for generic input/output, serial clock output, or serial clock input.
The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally
clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external
clock source is selected (CKE1 = 1). Select the SCI operating mode in SMR before setting the
CKE1 and CKE0 bits. For further details on selection of the SCI clock source, see table 13-9 in
section 13.3, Operation.
Bit 1
CKE1
0
0
1
1
Notes: 1. Initial value
then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0; or by clearing
the TEIE bit to 0.
2. The output clock frequency is the same as the bit rate.
3. The input clock frequency is 16 times the bit rate.
Description
Transmit-end interrupt requests (TEI) are disabled*
Transmit-end interrupt requests (TEI) are enabled*
Bit 0
CKE0
0
1
0
1
Description
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Internal clock, SCK pin available for generic
input/output
Internal clock, SCK pin used for serial clock output
Internal clock, SCK pin used for clock output
Internal clock, SCK pin used for serial clock output
External clock, SCK pin used for clock input
External clock, SCK pin used for serial clock input
External clock, SCK pin used for clock input
External clock, SCK pin used for serial clock input
432
*1
(Initial value)
*3
*3
*2
*1