D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 30

• Manufacturer Part Number: D13002F16V
• Description: IC H8/3002 ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13002F16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 1-3 Pin Functions (cont)
Type
System
control
Interrupts
Address
bus
Data bus
Bus control CS
Symbol
RES
RESO
STBY
BREQ
BACK
NMI
IRQ
IRQ
Modes
1 and 2 A
Modes
3 and 4 A
D
AS
RD
HWR
LWR
WAIT
15
3
5
0
to D
to CS
to
0
A
A
0
19
23
0
0
to 56 to 45,
to 100 to 97,
FP-100B,
TFP-100B
63
10
62
59
60
64
17, 16,
90 to 87
43 to 36
56 to 45,
43 to 36
34 to 23,
21 to 18
91 to 88
69
70
71
72
58
Pin No.
FP-100A
65
12
64
61
62
66
19, 18
92 to 89
58 to 47
45 to38
99, 100,
1, 2,
58 to 47
45 to 38
36 to 25
23 to 20
90 to 93
71
72
73
74
60
13
I/O
Input
Output
Input
Input
Output
Input
Input
Output
Input/
output
Output
Output
Output
Output
Output
Input
Name and Function
Reset input: When driven low, this pin
resets control the H8/3002
Reset output: Outputs the reset signal
generated by the watchdog timer to external
devices.
Standby: When driven low, this pin forces a
transition to hardware standby mode
Bus request: Used by an external bus
master to request the bus right from the
H8/3002
Bus request acknowledge: Indicates that
the bus has been granted to an external bus
master
Nonmaskable interrupt: Requests a
nonmaskable interrupt
Interrupt request 5 to 0: Maskable
interrupt request pins
Address bus: Outputs address signals
Data bus: Bidirectional data bus
Chip select: Select signals for areas 3 to 0
Address strobe: Goes low to indicate valid
address output on the address bus
Read: Goes low to indicate reading from the
external address space
High write: Goes low to indicate writing to
the external address space; indicates valid
data on the upper data bus (D
Low write: Goes low to indicate writing to
the external address space; indicates valid
data on the lower data bus (D
Wait: Requests insertion of wait states in
bus cycles during access to the external
address space
7
15
to D
to D
0
).
8
).