D13002F16V Renesas Electronics America, D13002F16V Datasheet - Page 252

• Manufacturer Part Number: D13002F16V
• Description: IC H8/3002 ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13002F16V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SCI
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.6.5 Note on Activating DMAC by Internal Interrupts
When using an internal interrupt to activate the DMAC, make sure that the interrupt selected as
the activating source does not occur during the interval after it has been selected but before the
DMAC has been enabled. The on-chip supporting module that will generate the interrupt should
not be activated until the DMAC has been enabled. If the DMAC must be enabled while the on-
chip supporting module is active, follow the procedure in figure 8-26.
If the DTE bit is set to 1 but the DTME bit is cleared to 0, the DMAC is halted and the selected
activating source cannot generate a CPU interrupt. If the DMAC is halted by an NMI interrupt, for
example, the selected activating source cannot generate CPU interrupts. To terminate DMAC
operations in this state, clear the DTE bit to 0 to allow CPU interrupts to be requested. To continue
DMAC operations, carry out steps 2 and 4 in figure 8-26 before and after setting the DTME bit
to 1.
Interrupt hand-
ling by CPU
Figure 8-26 Procedure for Enabling DMAC while On-Chip Supporting
Yes
Clear selected interrupt’s
Set selected interrupt’s
Enabling of DMAC
Selected interrupt
DMAC operates
enable bit to 0
Enable DMAC
enable bit to 1
requested?
Module is Operating (Example)
No
236
1
2
3
4
1.
2.
3.
4.
While the DTE bit is cleared to 0,
interrupt requests are sent to the
CPU.
Clear the interrupt enable bit to 0
in the interrupt-generating on-chip
supporting module.
Enable the DMAC.
Enable the DMAC-activating
interrupt.