EVAL-ADUC832QSZ Analog Devices Inc, EVAL-ADUC832QSZ Datasheet - Page 62

• Manufacturer Part Number: EVAL-ADUC832QSZ
• Description: KIT DEV FOR ADUC832 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC832QSZ

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC832
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: EVAL-ADUC832QS; EVAL-ADUC832QS

ADuC832
External Memory Interface
In addition to its internal program and data memories, the
ADuC832 can access up to 64 kBytes of external program memory
(ROM/PROM/and so on.) and up to 16 MBytes of external data
memory (SRAM).
To select from which code space (internal or external program
memory) to begin executing instructions, tie the EA (external
access) pin high or low, respectively. When EA is high (pulled
up to V
internal 62 kBytes Flash/EE code space. When EA is low (tied to
ground) user program execution will start at address 0 of the
external code space.
A second very important function of the EA pin is described
in the Single Pin Emulation Mode section.
External program memory (if used) must be connected to the
ADuC832 as illustrated in Figure 57. Note that 16 I/O lines
(Ports 0 and 2) are dedicated to bus functions during external
program memory fetches. Port 0 (P0) serves as a multiplexed
address/data bus. It emits the low byte of the program counter
(PCL) as an address, and then goes into a float state awaiting
the arrival of the code byte from the program memory. During
the time that the low byte of the program counter is valid on P0,
the signal ALE (Address Latch Enable) clocks this byte into an
address latch. Meanwhile, Port 2 (P2) emits the high byte of
the program counter (PCH), then PSEN strobes the EPROM
and the code byte is read into the ADuC832.
Note that program memory addresses are always 16 bits wide, even
in cases where the actual amount of program memory used is
less than 64 kBytes. External program execution sacrifices two of
the 8-bit ports (P0 and P2) to the function of addressing the pro-
gram memory. While executing from external program memory,
Ports 0 and 2 can be used simultaneously for read/write access
to external data memory, but not for general-purpose I/O.
Though both external program memory and external data memory
are accessed by some of the same pins, the two are completely
independent of each other from a software point of view. For
example, the chip can read/write external data memory while
executing from external program memory.
Figure 58 shows a hardware configuration for accessing up to
64 kBytes of external RAM. This interface is standard to any
8051 compatible MCU.
Figure 57. External Program Memory Interface
DD
ADuC832
), user program execution will start at address 0 of the
PSEN
ALE
P0
P2
LATCH
OE
D0–D7
(INSTRUCTION)
A8–A15
A0–A7
EPROM
–62–
If access to more than 64 kBytes of RAM is desired, a feature
unique to the ADuC832 allows addressing up to 16 MBytes of
external RAM simply by adding an additional latch, as illustrated
in Figure 59.
In either implementation, Port 0 (P0) serves as a multiplexed
address/data bus. It emits the low byte of the data pointer (DPL)
as an address, which is latched by a pulse of ALE prior to data
being placed on the bus by the ADuC832 (write operation) or the
SRAM (read operation). Port 2 (P2) provides the data pointer
page byte (DPP) to be latched by ALE, followed by the data
pointer high byte (DPH). If no latch is connected to P2, DPP is
ignored by the SRAM, and the 8051 standard of 64 kBytes
external data memory access is maintained.
Power Supplies
The ADuC832’s operational power supply voltage range is 2.7 V
to 5.25 V. Although the guaranteed data sheet specifications are
given only for power supplies within 2.7 V to 3.6 V or ± 10% of
the nominal 5 V level, the chip will function equally well at any
power supply level between 2.7 V and 5.5 V.
Note that Figures 60 and 61 refer to the PQFP package, for
the CSP package connect the extra DV
AGND in the same manner.
Figure 59. External Data Memory Interface (16 MBytes
Address Space)
Figure 58. External Data Memory Interface (64 K
Address Space)
ADuC832
ADuC832
ALE
ALE
WR
WR
RD
RD
P0
P2
P0
P2
LATCH
LATCH
LATCH
DD
, DGND, AV
A0–A7
A0–A7
A8–A15
A16–A23
OE
WE
D0–D7
(DATA)
A8–A15
OE
WE
D0–D7
(DATA)
SRAM
SRAM
DD
, and
REV. 0