EVAL-ADUC832QSZ Analog Devices Inc, EVAL-ADUC832QSZ Datasheet - Page 17

• Manufacturer Part Number: EVAL-ADUC832QSZ
• Description: KIT DEV FOR ADUC832 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC832QSZ

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC832
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: EVAL-ADUC832QS; EVAL-ADUC832QS

SPECIAL FUNCTION REGISTERS
All registers except the program counter and the four general-
purpose register banks reside in the special function register
(SFR) area. The SFR registers include control, configuration,
and data registers that provide an interface between the CPU
and other on-chip peripherals.
Figure 6 shows a full SFR memory map and SFR contents on
Reset. Unoccupied SFR locations are shown dark-shaded in
SFR MAP KEY:
1
2
3
REV. 0
NOTES
EFH
FFH
F7H
E7H
DFH
D7H
CFH
C7H
BFH
B7H
AFH
A7H
9FH
97H
8FH
87H
SFRs WHOSE ADDRESS ENDS IN 0H OR 8H ARE BIT ADDRESSABLE.
THE PRIMARY FUNCTION OF PORT1 IS AS AN ANALOG INPUT PORT; THEREFORE, TO ENABLE THE DIGITAL SECONDARY FUNCTIONS ON THESE
CALIBRATION COEFFICIENTS ARE PRECONFIGURED ON POWER-UP TO FACTORY CALIBRATED VALUES.
PORT PINS, WRITE A “0” TO THE CORRESPONDING PORT 1 SFR BIT.
PRE3
ADCI
MDO
SM0
ISPI
TF2
PSI
TF1
RD
CY
EA
0
0 F6H
0 EEH
0 E6H
0
0
0
0
0
1
0
0
1 96H
0
1 86H
1
FEH
DEH
D6H
CEH
C6H
BEH
B6H
AEH
A6H
9EH
8EH
WCOL
PADC
EADC
PRE2
EXF2
DMA
MDE
SM1
TR1
WR
AC
0
0 F5H
0
0 E5H
0
0
0
0
0
1
0
0
1 95H
0
1 85H
1
CCONV
FDH
EDH
DDH
D5H
CDH
C5H
BDH
B5H
ADH
A5H
9DH
8DH
RCLK
PRE1
MCO
SM2
SPE
PT2
ET2
TF0
F0
T1
0
0
0 F4H
0 ECH
0 E4H
0
0
0
0 C4H
0
1
1 A4H
0
1 94H
0
1 84H
FCH
SCONV
DCH
D4H
CCH
BCH
B4H
ACH
9CH
8CH
TCLK
PRE0
SPIM
REN
MDI
RS1
TR0
PS
ES
T0
0
0 F3H
0 EBH
0 E3H
0
0
0
1
0
1
0
1 A3H
0
1 93H
0
1 83H
FBH
DBH
D3H
CBH
C3H
BBH
B3H
ABH
9BH
8BH
EXEN2
CPOL
WDIR
I2CM
INT1
CS3
RS0
PT1
ET1
TB8
IE1
DEFAULT VALUE
SFR ADDRESS
Figure 6. Special Function Register Locations and Reset Values
0
0 F2H
0 EAH
0 E2H
0
0
0
0
0
1
0
1 A2H
0
1 92H
0
1 82H
MNEMONIC
FAH
DAH
D2H
CAH
C2H
BAH
B2H
AAH
9AH
8AH
CPHA
I2CRS
WDS
INT0
RB8
CS2
TR2
PX1
EX1
OV
IT1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
F9H
F1H
E9H
E1H
D9H
D1H
C9H
C1H
B9H
B1H
A9H
A1H
99H
91H
89H
81H
I2CTX
SPR1
CNT2
T2EX
WDE
CS1
PT0
TxD
ET0
IE0
FI
TI
THESE BITS ARE CONTAINED IN THIS BYTE.
0
0 F0H
0 E8H
0 E0H
0
0
0
0
0
1
0
1 A0H
0
1
0
1 80H
F8H
D8H
D0H
C8H
C0H
B8H
B0H
A8H
98H
90H
88H
WDWR
SPR0
CAP2
I2CI
CS0
PX0
RxD
EX0
IT0
T2
89H
RI
P
IE0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
88H
IT0
0
ADCCON2
E0H
D8H
D0H
C8H
C0H
B0H
B8H
A8H
A0H
98H
F8H
F0H
E8H
90H
88H
80H
SPICON
I2CCON
WDCON
T2CON
SCON
TCON
ACC
PSW
P1
–17–
P3
P2
P0
IP
IE
B
1, 2
1
88H
1
1
00H
FFH
00H
FFH
00H
FFH
1
1
1
FFH
04H
00H
00H
00H
00H
00H
00H
10H
1
00H
TCON
1
1
1
1
1
1
1
the figure below (NOT USED). Unoccupied locations in the
SFR address space are not implemented i.e., no register exists
at this location. If an unoccupied location is read, an unspecified
value is returned. SFR locations reserved for on-chip testing are
shown lighter shaded below (RESERVED) and should not be
accessed by user software. Sixteen of the SFR locations are also
bit addressable and denoted by
bit addressable SFRs are those whose address ends in 0H or 8H.
1
00H
ADCDATAL
ADCOFSL
B1H
RESERVED
TIMECON
A1H
F9H
F1H
RESERVED
RESERVED
D9H
RESERVED
B9H
A9H
99H
89H
81H
RESERVED
NOT USED
PWM0L
DAC0L
ECON
TMOD
SBUF
IEIP2
SP
A0H
00H
00H
00H
00H
00H
00H
07H
00H
00H
3
MNEMONIC
DEFAULT VALUE
SFR ADDRESS
ADCOFSH
ADCDATAH
B2H
RESERVED
A2H
FAH
F2H
RESERVED
RESERVED
DAH
D2H
CAH
RESERVED
9AH
8AH
82H
C2H
HTHSEC
NOT USED
RCAP2L
PWM0H
I2CDAT
DAC0H
CHIPID
DMAL
DPL
TL0
00H
20H
00H
00H
00H
2XH
00H
00H
00H
00H
00H
3
ADCGAINL
B3H
9BH
A3H
FBH
F3H
RESERVED
RESERVED
RESERVED
D3H
CBH
RESERVED
RESERVED
8BH
83H
RESERVED
NOT USED
RCAP2H
PWM1L
I2CADD
DAC1L
SEC
DMAH
DPH
TL1
00H
00H
00H
00H
00H
00H
00H
55H
00H
3
ADCGAINH
B4H
RESERVED
FCH
F4H
RESERVED
RESERVED
RESERVED
D4H
CCH
RESERVED
BCH
8CH
84H
A4H
NOT USED
NOT USED
EDATA1
PWM1H
DAC1H
DMAP
MIN
TH0
DPP
TL2
'1'
00H
00H
00H
00H
00H
00H
00H
00H
00H
in the figure below, i.e., the
3
ADCCON3
9DH
FDH
F5H
RESERVED
RESERVED
RESERVED
RESERVED
CDH
RESERVED
BDH
RESERVED
8DH
DACCON
NOT USED
A5H
NOT USED
RESERVED
EDATA2
HOUR
T3FD
TH2
TH1
04H
00H
00H
00H
00H
00H
00H
ADuC832
9EH
AEH
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
C6H
BEH
PWMCON
NOT USED
A6H
NOT USED
RESERVED
EDATA3
T3CON
EDARL
INTVAL
00H
00H
00H
00H
00H
D7H
AFH
ADCCON1
B7H
A7H
RESERVED
F7H
EFH
RESERVED
DFH DEH
RESERVED
C7H
BFH
RESERVED
87H
PSMCON
NOT USED
NOT USED
PLLCON
EDATA4
CFG832
SPIDAT
EDARH
DPCON
PCON
SPH
00H
00H
00H
00H
00H
53H
00H
00H
00H