EVAL-ADUC832QSZ Analog Devices Inc, EVAL-ADUC832QSZ Datasheet - Page 36

• Manufacturer Part Number: EVAL-ADUC832QSZ
• Description: KIT DEV FOR ADUC832 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC832QSZ

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC832
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: EVAL-ADUC832QS; EVAL-ADUC832QS

ADuC832
PULSEWIDTH MODULATOR (PWM)
The PWM on the ADuC832 is a highly flexible PWM offering
programmable resolution and an input clock, and can be config-
ured for any one of six different modes of operation. Two of
these modes allow the PWM to be configured as a - DAC
with up to 16 bits of resolution. A block diagram of the PWM is
shown in Figure 26.
Bit
7
6
5
4
3
2
1
0
TO/EXTERNAL PWM CLOCK
Name
SNGL
MD2
MD1
MD0
CDIV1
CDIV0
CSEL1
CSEL0
Figure 26. PWM Block Diagram
f
XTAL
f
XTAL
f
VCO
/15
Turns off PWM Output at P2.6 or P3.4 Leaving Port Pin Free for Digital I/O.
PWM Mode Bits
The MD2/1/0 bits choose the PWM mode as follows:
MD2
0
0
0
0
1
1
1
1
PWM Clock Divider
Scale the clock source for the PWM counter as shown below:
CDIV1 CDIV0 Description
0
0
1
1
PWM Clock Divider
Select the clock source for the PWM as shown below:
CSEL1 CSEL0 Description
0
0
1
1
Description
SELECT
CLOCK
MODE
16-BIT PWM COUNTER
MD1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PROGRAMMABLE
COMPARE
PWM0H/L
DIVIDER
Table XI. PWMCON SFR Bit Designations
MD0
0
1
0
1
0
1
0
1
PWM Counter = Selected Clock /1
PWM Counter = Selected Clock /4
PWM Counter = Selected Clock /16
PWM Counter = Selected Clock /64
PWM Clock = f
PWM Clock = f
PWM Clock = External input at P3.4/T0
PWM Clock = f
PWM1H/L
Mode
Mode 0: PWM Disabled
Mode 1: Single variable resolution PWM on P2.7 or P3.3
Mode 2: Twin 8-bit PWM
Mode 3: Twin 16-bit PWM
Mode 4: Dual NRZ 16-bit - DAC
Mode 5: Dual 8-bit PWM
Mode 6: Dual RZ 16-bit - DAC
Reserved for future use
P2.6
P2.7
XTAL
XTAL
VCO
–36–
= 16.777216 MHz
/15
The PWM uses five SFRs: the control SFR (PWMCON) and
four data SFRs (PWM0H, PWM0L, PWM1H, and PWM1L).
PWMCON (as described below) controls the different modes of
operation of the PWM as well as the PWM clock frequency.
PWM0H/L and PWM1H/L are the data registers that deter-
mine the duty cycles of the PWM outputs. The output pins that
the PWM uses are determined by the CFG832 register, and can
be either P2.6 and P2.7 or P3.4 and P3.3. In this section of the
data sheet, it is assumed that P2.6 and P2.7 are selected as the
PWM outputs.
To use the PWM user software, first write to PWMCON to
select the PWM mode of operation and the PWM input clock.
Writing to PWMCON also resets the PWM counter. In any of
the 16-bit modes of operation (modes 1, 3, 4, 6), user software
should write to the PWM0L or PWM1L SFRs first. This value
is written to a hidden SFR. Writing to the PWM0H or PWM1H
SFRs updates both the PWMxH and the PWMxL SFRs but
does not change the outputs until the end of the PWM cycle in
progress. The values written to these 16-bit registers are then
used in the next PWM cycle.
PWMCON
SFR Address
Power-On Default Value
Bit Addressable
PWM Control SFR
AEH
00H
No
REV. 0