EVAL-ADUC832QSZ Analog Devices Inc, EVAL-ADUC832QSZ Datasheet - Page 19

• Manufacturer Part Number: EVAL-ADUC832QSZ
• Description: KIT DEV FOR ADUC832 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC832QSZ

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC832
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: EVAL-ADUC832QS; EVAL-ADUC832QS

ADCCON1 – (ADC Control SFR #1)
The ADCCON1 register controls conversion and acquisition
times, hardware conversion modes, and power-down modes as
detailed below.
SFR Address:
SFR Power-On Default Value:
Bit Addressable:
Bit
ADCCON1.7
ADCCON1.6
ADCCON1.5
ADCCON1.4
ADCCON1.3
ADCCON1.2
ADCCON1.1 T2C
ADCCON1.0 EXC
REV. 0
Name
MD1
EXT_REF
CK1
CK0
AQ1
AQ0
Description
The Mode bit selects the active operating mode of the ADC.
Set by the user to power up the ADC.
Cleared by the user to power down the ADC.
Set by the user to select an external reference.
Cleared by the user to use the internal reference.
The ADC clock divide bits (CK1, CK0) select the divide ratio for the PLL master clock used to generate the
ADC clock. To ensure correct ADC operation, the divider ratio must be chosen to reduce the ADC clock
to 4.5 MHz and below. A typical ADC conversion will require 17 ADC clocks.
The divider ratio is selected as follows:
CK1
0
0
1
1
The ADC acquisition select bits (AQ1, AQ0) select the time provided for the input track-and-hold amplifier
to acquire the input signal. An acquisition of three or more ADC clocks is recommended; clocks are
selected as follows:
AQ1 AQ0 #ADC Clks
0
0
1
1
The Timer 2 conversion bit (T2C) is set by the user to enable the Timer 2 overflow bit be used as
the ADC convert start trigger input.
The external trigger enable bit (EXC) is set by the user to allow the external Pin P3.5 (CONVST) to
be used as the active low convert start input. This input should be an active low pulse (minimum
pulsewidth >100 ns) at the required sample rate.
EFH
00H
NO
CK0 MCLK Divider
0
1
0
1
0
1
0
1
Table III. ADCCON1 SFR Bit Designations
8
4
16
32
1
2
3
4
–19–
ADuC832