EVAL-ADUC832QSZ Analog Devices Inc, EVAL-ADUC832QSZ Datasheet - Page 39

• Manufacturer Part Number: EVAL-ADUC832QSZ
• Description: KIT DEV FOR ADUC832 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC832QSZ

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC832
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: EVAL-ADUC832QS; EVAL-ADUC832QS

SERIAL PERIPHERAL INTERFACE
The ADuC832 integrates a complete hardware Serial Peripheral
Interface (SPI) on-chip. SPI is an industry standard synchronous
serial interface that allows eight bits of data to be synchronously
transmitted and received simultaneously, i.e., full duplex. It should
be noted that the SPI pins are shared with the I
the user can only enable one or the other interface at any given
time (see SPE in Table XII). The SPI port can be configured for
Master or Slave operation and typically consists of four pins, namely:
MISO (Master In, Slave Out Data I/O Pin)
The MISO (master in slave out) pin is configured as an input line
in master mode and an output line in slave mode. The MISO line
on the master (data in) should be connected to the MISO line
in the slave device (data out). The data is transferred as byte
wide (8-bit) serial data, MSB first.
MOSI (Master Out, Slave In Pin)
The MOSI (master out slave in) pin is configured as an output
line in master mode and an input line in slave mode. The MOSI
line on the master (data out) should be connected to the MOSI
line in the slave device (data in). The data is transferred as byte
wide (8-bit) serial data, MSB first.
SCLOCK (Serial Clock I/O Pin)
The master serial clock (SCLOCK) is used to synchronize the
data being transmitted and received through the MOSI and MISO
data lines. A single data bit is transmitted and received in each
SPICON
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
The CPOL and CPHA bits should both contain the same values for master and slave devices.
REV. 0
Name
ISPI
WCOL
SPE
SPIM
CPOL
CPHA
SPR1
SPR0
SPI Control Register
F8H
O4H
Yes
Description
SPI Interrupt Bit.
Set by MicroConverter at the end of each SPI transfer.
Cleared directly by user code or indirectly by reading the SPIDAT SFR.
Write Collision Error Bit.
Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress.
Cleared by user code.
SPI Interface Enable Bit.
Set by user to enable the SPI interface.
Cleared by user to enable the I
SPI Master/Slave Mode Select Bit.
Set by user to enable Master Mode operation (SCLOCK is an output).
Cleared by user to enable Slave Mode operation (SCLOCK is an input).
Clock Polarity Select Bit.
Set by user if SCLOCK idles high.
Cleared by user if SCLOCK idles low.
Clock Phase Select Bit.
Set by user if leading SCLOCK edge is to transmit data.
Cleared by user if trailing SCLOCK edge is to transmit data.
SPI Bit-Rate Select Bits.
These bits select the SCLOCK rate (bitrate) in master mode as follows:
SPR1
0
0
1
1
In SPI Slave Mode, i.e., SPIM = 0, the logic level on the external SS pin can be read via the SPR0 bit.
Table XII. SPICON SFR Bit Designations
2
C pins. Therefore,
SPR0
0
1
0
1
Selected Bit Rate
f
f
f
f
OSC
OSC
OSC
OSC
–39–
/2
/4
/8
/16
2
C pins.
SCLOCK period. Therefore, a byte is transmitted/received after
eight SCLOCK periods. The SCLOCK pin is configured as an
output in master mode and as an input in slave mode. In master
mode the bit-rate, polarity, and phase of the clock are controlled
by the CPOL, CPHA, SPR0, and SPR1 bits in the SPICON SFR
(see Table XII). In slave mode the SPICON register will have to
be configured with the phase and polarity (CPHA and CPOL) of
the expected input clock. In both master and slave modes the
data is transmitted on one edge of the SCLOCK signal and sampled
on the other. It is important therefore that the CPHA and CPOL
are configured the same for the master and slave devices.
SS (Slave Select Input Pin)
The Slave Select (SS) input pin is shared with the ADC5 input.
In order to configure this pin as a digital input, the bit must be
cleared, e.g., CLR P1.5.
This line is active low. Data is only received or transmitted in
slave mode when the SS pin is low, allowing the ADuC832 to be
used in single master, multislave SPI configurations. If CPHA = 1
then the SS input may be permanently pulled low. With CPHA = 0,
the SS input must be driven low before the first bit in a byte
wide transmission or reception and return high again after the
last bit in that byte wide transmission or reception. In SPI slave
mode, the logic level on the external SS pin can be read via the
SPR0 bit in the SPICON SFR.
The following SFR registers are used to control the SPI interface.
ADuC832