EVAL-ADUC832QSZ Analog Devices Inc, EVAL-ADUC832QSZ Datasheet - Page 59

• Manufacturer Part Number: EVAL-ADUC832QSZ
• Description: KIT DEV FOR ADUC832 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC832QSZ

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC832
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: EVAL-ADUC832QS; EVAL-ADUC832QS

Timer 3 Generated Baud Rates
The high integer dividers in a UART block mean that high speed
baud rates are not always possible using some particular crystals.
For example, using a 12 MHz crystal, a baud rate of 115200 is
not possible. To address this problem, the ADuC832 has added
a dedicated baud rate timer (Timer 3) specifically for generating
highly accurate baud rates.
Timer 3 can be used instead of Timer 1 or Timer 2 for generating
very accurate high speed UART baud rates including 115200
and 230400. Timer 3 also allows a much wider range of baud
rates to be obtained. In fact, every desired bit rate from 12 bit/s
to 393216 bit/s can be generated to within an error of ± 0.8%.
Timer 3 also frees up the other three timers, allowing them to
be used for different applications. A block diagram of Timer 3
is shown in Figure 54.
Two SFRs (T3CON and T3FD) are used to control Timer 3.
T3CON is the baud rate control SFR, allowing Timer 3 to be
used to set up the UART baud rate, and setting up the binary
divider (DIV).
Bit
REV. 0
7
6
5
4
3
2
1
0
FRACTIONAL
*CORE CLK IS DEFINED BY THE CD BITS IN PLLCON
DIVIDER
CORE
CLK*
Table XXVII. T3CON SFR Bit Designations
Name
T3BAUDEN
DIV2
DIV1
DIV0
Figure 54. Timer 3, UART Baud Rates
(1 + T3FD/64)
2
16
DIV
2
T3 RX/TX
CLOCK
Description
T3UARTBAUD Enable
Set to enable Timer 3 to generate
the baud rate. When set PCON.7,
T2CON.4 and T2CON.5 are ignored.
Cleared to let the baud rate be
generated as per a standard 8052.
Binary Divider Factor
DIV2 DIV1 DIV0 Bin Divider
-
-
-
-
0
0
0
0
1
1
1
1
RX CLOCK (FIG 53)
TIMER 1/TIMER 2
1
1
0
0
1
1
0
0
1
1
TX CLOCK (FIG 53)
0
0
TIMER 1/TIMER 2
0
1
0
1
0
1
0
1
T3EN
1
1
1
1
1
1
1
1
TX CLOCK
RX
CLOCK
–59–
The appropriate value to write to the DIV2-1-0 bits can be calculated
using the following formula where f
Note: The DIV value must be rounded down.
T3FD is the fractional divider ratio required to achieve the
required baud rate. We can calculate the appropriate value for
T3FD using the following formula:
Note: T3FD should be rounded to the nearest integer.
Once the values for DIV and T3FD are calculated the actual
baud rate can be calculated using the following formula:
For example, to get a baud rate of 115200 while operating at
16.7 MHz
therefore, the actual baud rate is 114912 bit/s.
Ideal
Baud
230400
115200
115200
115200
57600
57600
57600
57600
38400
38400
38400
38400
19200
19200
19200
19200
19200
9600
9600
9600
9600
9600
9600
Table XXVIII. Commonly Used Baud Rates Using Timer 3
T FD
DIV
3
=
=
LOG
CD
0
0
1
2
0
1
2
3
0
1
2
3
0
1
2
3
4
0
1
2
3
4
5
Actual Baud Rate =
(
2 11059200
×
(
11059200 32 115200
DIV
T FD
DIV
1
2
1
0
3
2
1
0
3
2
1
0
4
3
2
1
0
5
4
3
2
1
0
3
=
log
=
)
2
/
/



DIV
(
(
32
2
1
2
2
×
T3CON
81H
82H
81H
80H
83H
82H
81H
80H
83H
82H
81H
80H
84H
83H
82H
81H
80H
85H
84H
83H
82H
81H
80H
log( )
×
×
×
DIV
CORE
×
115200
Baud Rate
Baud Rate
f
CORE
f
CORE
2
2
×
defined in PLLCON SFR:
(
×
T FD
3
f
)
CORE
)
–
)
/
ADuC832



64
LOG
T3FD
09H
09H
09H
09H
09H
09H
09H
09H
2DH
2DH
2DH
2DH
2DH
2DH
2DH
2DH
2DH
2DH
2DH
2DH
2DH
2DH
2DH
+
=
64
32 20
2 1 58 1
)
=
=
.
%
Error
0.25
0.25
0.25
0.25
0.25
0.25
0.25
0.25
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
H
=