M3062PT3-RPD-E Renesas Electronics America, M3062PT3-RPD-E Datasheet - Page 77

• Manufacturer Part Number: M3062PT3-RPD-E
• Description: EMULATOR BASE UNIT FOR M16C/60
• Manufacturer: Renesas Electronics America

Specifications of M3062PT3-RPD-E

• Accessory Type: Emulation Pod
• For Use With/related Products: PC4701, M16C/60, M16C/30
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: M3062PT3-RPD#E; M3062PT3-RPD#E

REJ10J0040-0600 Rev.6.00 July 01, 2006
M3062PT3-RPD-E User’s Manual
(2) Multiplex Bus Timing
Table 4.3 and Figure 4.2 show the bus timing in memory expansion mode and microprocessor mode (2 wait, accessing external
area, using multiplex bus).
Table 4.3 Memory expansion mode and microprocessor mode (2 wait, accessing external area, using multiplex bus)
*1 Calculated by the following formula according to the frequency of BCLK.
*2 Calculated by the following formula according to the frequency of BCLK.
*3 Calculated by the following formula according to the frequency of BCLK.
*4 Calculated by the following formula according to the frequency of BCLK.
(
f
f
f
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(ALE-AD)
td(AD-RD)
td(AD-WR)
tdz(RD-AD)
n
0.5
0.5
0.5
f
(
(
(
BCLK
−
BCLK
BCLK
(
BCLK
×
×
0.5
×
Symbol
10
10
10
)
9
9
9
×
)
)
)
10
−
)
−
−
9
10
15
25
−
40
[ns]
[ns]
[ns]
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip-select output delay time
Chip-select output hold time (BCLK standard)
Chip-select output hold time (RD standard)
Chip-select output hold time (WR standard)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)
ALE output delay time (BCLK standard)
ALE output hold time (BCLK standard)
ALE output delay time (Address standard)
ALE output hold time (Address standard)
After address RD signal output delay time
After address WR signal output delay time
Address output floating start time
[ns] n: "2" for 2 wait
Item
Min.
(*1)
(*1)
(*1)
(*3)
(*4)
(*1)
(*1)
(*2)
-4
Actual MCU
4
4
0
0
4
0
0
[ns]
Max.
25
25
25
25
40
25
8
4. Hardware Specifications
See left
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Min.
-1
-4
-4
-3
This product
[ns]
Page 75 of 104
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Max.
26
17