MT46H8M32LFB5-6:A TR Micron Technology Inc, MT46H8M32LFB5-6:A TR Datasheet - Page 77

• Manufacturer Part Number: MT46H8M32LFB5-6:A TR
• Description: IC DDR SDRAM 256MBIT 90VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H8M32LFB5-6:A TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 120mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1280-2; MT46H8M32LFB5-6:A TR

Figure 49:
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
Command
BA0, BA1
A11, A12
A0–A9
DQS
DQ
CK#
CKE
A10
DM
CK
1
5
t
t
IS
IS
Write – DM Operation
NOP 6
T0
t
t
IH
IH
Notes:
t
t
Bank x
IS
IS
ACT
RA
RA
T1
RA
1. D
2. BL = 4 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T5.
5. PRE = PRECHARGE; ACT = ACTIVE; RA = row address; BA = bank address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these
7.
8.
t
t
IH
IH
t
order.
times.
t
t
CK
DSH is applicable during
DSS is applicable during
IN
n = data-in from column n; subsequent elements are provided in the programmed
t
t
RCD
RAS
NOP 6
T2
t
CH
t
CL
t
WRITE 2
Bank x
IS
Col n
3
T3
t
t
IH
DQSS (NOM)
t
WPRES
t
t
DQSS (MIN) and is referenced from CK T5 or T6.
DQSS (MIN) and is referenced from CK T4 or T5.
t
77
DS
t
WPRE
NOP 6
D
T4
OUT
b
t
DH
T4n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile DDR SDRAM
t
DQSL
NOP 6
T5
t
DQSH
T5n
t
WPST
Transitioning data
NOP 6
T6
©2005 Micron Technology, Inc. All rights reserved.
Timing Diagrams
t WR
NOP 6
T7
Don’t Care
One bank
All banks
Bank x 4
T8
PRE
t RP