MT46H8M32LFB5-6:A TR Micron Technology Inc, MT46H8M32LFB5-6:A TR Datasheet - Page 74

• Manufacturer Part Number: MT46H8M32LFB5-6:A TR
• Description: IC DDR SDRAM 256MBIT 90VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H8M32LFB5-6:A TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 120mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1280-2; MT46H8M32LFB5-6:A TR

Figure 46:
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
Case 1:
Case 2:
Command
BA0, BA1
A11, A12
A0–A9
t
DQS
t
DQS
CK#
CKE
A10
DQ
DQ
DM
AC (MIN) and
AC (MAX) and
CK
1
1
5
Bank Read – with Auto Precharge
t
t
IS
IS
NOP
T0
t
DQSCK (MIN)
t
t
DQSCK (MAX)
6
t
IH
IH
Notes:
Bank x
t
t
IS
IS
ACT
RA
RA
T1
RA
8. Refer to Figures 37 and 38 on pages 66–67 for DQS and DQ timing details.
1. D
2. BL = 4 in the case shown.
3. Enable auto precharge.
4. “Don’t Care” if A10 is HIGH at T5.
5. PRE = PRECHARGE; ACT = ACTIVE; RA = row address; BA = bank address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these
t
t
IH
IH
t
times.
CK
OUT
t
t
RAS
RCD
t
RC
n = data-out from column n.
NOP
T2
6
t
CH
t
CL
t
3
IS
Bank x
READ
Col n
t
LZ (MIN)
T3
2
t
IH
t
CL = 2
RPRE
74
t
t
LZ (MIN)
AC (MIN)
NOP
T4
6
t
AC (MAX)
t
D
RPRE
OUT
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile DDR SDRAM
t
DQSCK (MIN)
NOP
D
n + 1
T5
OUT
D
t
OUT
n
6
DQSCK (MAX)
T5n
D
n + 2
OUT
D
n + 1
OUT
t
RP
NOP
Transitioning data
D
n + 3
T6
t
D
n + 2
RPST
OUT
OUT
6
T6n
t
HZ (MAX)
D
n + 3
t
RPST
OUT
©2005 Micron Technology, Inc. All rights reserved.
NOP
T7
Timing Diagrams
6
Don’t Care
Bank x
ACT
T8
RA
RA
RA