MT46H8M32LFB5-6:A TR Micron Technology Inc, MT46H8M32LFB5-6:A TR Datasheet - Page 71

• Manufacturer Part Number: MT46H8M32LFB5-6:A TR
• Description: IC DDR SDRAM 256MBIT 90VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H8M32LFB5-6:A TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 120mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1280-2; MT46H8M32LFB5-6:A TR

Figure 43:
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
Command
BA0, BA1
A11, A12
A0–A9,
DQ
DQS
CK#
CKE
A10
DM
CK
5
1
1
1
1
5
5
Auto Refresh Mode
t
t
IS
NOP
IS
T0
t
2
IH
t
Notes:
IH
All banks
One bank
t
Bank(s)
IS
PRE
T1
1. PRE = PRECHARGE; ACT = ACTIVE; AR = AUTO REFRESH; RA = row address; BA = bank
2. NOP commands are shown for ease of illustration; other valid commands may be possible at
3. NOP or COMMAND INHIBIT are the only commands allowed until after
4. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active
5. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
6. The second AUTO REFRESH is not required and is only shown as an example of two back-to-
t
IH
4
CK
address.
these times. CKE must be active during clock positive transitions.
be active during clock positive transitions.
(for example, must precharge all active banks).
back AUTO REFRESH commands.
VALID
NOP
T2
2
t
CH
t RP
t
CL
NOP
T3
2
T4
AR
71
(
(
(
(
(
(
(
(
(
(
)
)
)
(
)
(
(
)
)
(
)
)
)
)
(
(
(
(
)
) )
) )
)
)
)
)
)
)
)
(
(
(
(
(
(
(
(
(
(
(
)
)
)
(
)
(
(
)
)
(
)
(
)
(
)
(
)
)
)
)
)
)
)
)
)
t RFC
NOP
Ta0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile DDR SDRAM
2, 3
Ta1
AR
6
(
(
(
(
(
(
(
(
(
(
)
)
)
)
)
)
)
)
)
)
(
(
(
(
(
(
(
(
(
)
) )
)
)
)
)
)
)
)
)
(
(
(
(
(
(
(
(
(
(
(
)
)
(
)
(
)
(
(
)
)
(
)
(
)
(
)
(
)
)
)
)
)
)
)
)
)
)
VALID
NOP
Tb0
2, 3
©2005 Micron Technology, Inc. All rights reserved.
t RFC
Timing Diagrams
6
NOP
Tb1
t
2
RFC time; CKE must
Don’t Care
Tb2
ACT
BA
RA
RA