MT46H8M32LFB5-6:A TR Micron Technology Inc, MT46H8M32LFB5-6:A TR Datasheet - Page 73

• Manufacturer Part Number: MT46H8M32LFB5-6:A TR
• Description: IC DDR SDRAM 256MBIT 90VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H8M32LFB5-6:A TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 120mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1280-2; MT46H8M32LFB5-6:A TR

Figure 45:
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
Case 1:
Case 2:
Command
BA0, BA1
A11–Ai
A0–A9
t
t
AC (MIN) and
DQS
AC (MAX) and
DQS
DQ
DQ
CK#
CKE
A10
DM
CK
1
1
5
9
Bank Read – Without Auto Precharge
t
t
IS
IS
NOP
T0
Notes:
t
DQSCK (MIN)
t
DQSCK (MAX)
t
t
6
IH
IH
1. D
2. BL = 4 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T5.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = row address, and BA = bank address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these
7. The PRECHARGE command can only be applied at T5 if
t
IS
Bank x
t
IS
ACT
RA
T1
RA
RA
times.
t
IH
t
OUT
IH
t
CK
n = data-out from column n.
t
t
RAS
RCD
t
RC
NOP
7
T2
6
t
CH
t
CL
Bank x
t
t
READ
IS
LZ (MIN)
Col n
3
T3
2
t
IH
73
CL = 2
t
RPRE
t
t
AC (MIN)
LZ (MIN)
NOP
T4
5
t
AC (MAX)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D
t
256Mb: x16, x32 Mobile DDR SDRAM
OUT
RPRE
n
t
DQSCK (MIN)
One bank
All banks
Bank x
D
n + 1
PRE
OUT
T5
D
t
OUT
DQSCK (MAX)
n
7
4
D
n + 2
T5n
OUT
D
n + 1
OUT
t
Transitioning data
RAS minimum is met.
D
n + 3
NOP
t
OUT
T6
RPST
D
n + 2
OUT
6
t
RP
T6n
t
©2005 Micron Technology, Inc. All rights reserved.
HZ (MAX)
t
D
n + 3
RPST
OUT
Timing Diagrams
NOP
T7
6
Don’t Care
Bank x
ACT
T8
RA
RA
RA