MT46H8M32LFB5-6:A TR Micron Technology Inc, MT46H8M32LFB5-6:A TR Datasheet - Page 41

• Manufacturer Part Number: MT46H8M32LFB5-6:A TR
• Description: IC DDR SDRAM 256MBIT 90VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H8M32LFB5-6:A TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 120mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1280-2; MT46H8M32LFB5-6:A TR

Figure 26:
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
Command
Address
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
WRITE-to-READ – Uninterrupting
Bank a,
WRITE
Notes:
Col b
T0
t
DQSS
t
DQSS
t
DQSS
1. D
2. An uninterrupted burst of 4 is shown.
3.
4. The READ and WRITE commands are to the same bank. However, the READ and WRITE
5. A10 is LOW with the WRITE command (auto precharge is disabled).
D
b
t
commands can be directed to different banks in which case
READ command could be applied earlier.
IN
WTR is referenced from the first positive CK edge after the last data-in pair.
IN
NOP
D
T1
b
b = data-in for column b; D
IN
b+1
D
D
b
IN
IN
T1n
b+1
D
IN
b+2
b+1
D
D
IN
IN
b+2
NOP
D
T2
IN
b+2
b+3
D
D
IN
IN
b+3
T2n
D
IN
b+3
D
41
IN
NOP
T3
OUT
t
WTR
n = data-out for column n.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile DDR SDRAM
Bank a,
READ
Col n
T4
Transitioning data
CL = 2
CL = 2
CL = 2
T5
NOP
t
WTR is not required, and the
©2005 Micron Technology, Inc. All rights reserved.
T5n
D
D
D
OUT
n
OUT
OUT
n
n
T6
NOP
Don’t Care
Operations
D
D
D
n+1
n+1
n+1
OUT
OUT
OUT
T6n