MT46H8M32LFB5-6:A TR Micron Technology Inc, MT46H8M32LFB5-6:A TR Datasheet - Page 35

• Manufacturer Part Number: MT46H8M32LFB5-6:A TR
• Description: IC DDR SDRAM 256MBIT 90VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H8M32LFB5-6:A TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 120mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1280-2; MT46H8M32LFB5-6:A TR

Figure 20:
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
Command
Command
Address
Address
READ-to-PRECHARGE
DQS
DQS
CK#
CK#
DQ
DQ
CK
CK
Notes:
5
5
Bank a,
Bank a ,
READ
READ
Col n
Col n
T0
T0
1. D
2. BL = 4 or an interrupted burst of 8.
3. Shown with nominal
4. READ-to-PRECHARGE equals 2 clock cycles, which allows 2 data pairs of data-out.
5. A READ command with auto precharge enabled, provided
6. PRE = PRECHARGE command; ACT = ACTIVE command.
precharge to be performed at x number of clock cycles after the READ command, where x =
BL/2.
OUT
CL = 2
n = data-out from column n.
NOP
NOP
T1
T1
CL = 3
T1n
T1n
t
AC,
(a or all)
Bank a,
( a or all )
D
Bank a ,
OUT
n
T2
PRE
T2
PRE
t
DQSCK, and
35
D
n+1
T2n
T2n
OUT
D
OUT
n
D
n+2
T3
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
NOP
t
OUT
256Mb: x16, x32 Mobile DDR SDRAM
DQSQ.
Transitioning data
t RP
t RP
D
n+1
T3n
T3n
OUT
D
n+3
OUT
D
n+2
OUT
T4
T4
NOP
NOP
D
t
n+3
RAS (MIN) is met, would cause a
OUT
©2005 Micron Technology, Inc. All rights reserved.
Bank a ,
Bank a,
T5
T5
ACT
Row
ACT
Row
Don’t Care
Operations