W971GG6JB-25 Winbond Electronics, W971GG6JB-25 Datasheet - Page 7

• Manufacturer Part Number: W971GG6JB-25
• Description: IC DDR2-800 SDRAM 1GB 84-WBGA
• Manufacturer: Winbond Electronics

Specifications of W971GG6JB-25

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 2.5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-WBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5804012

5. BALL DESCRIPTION
M8,M3,M7,N2,N8,N3
,N7,P2,P8,P3,M2,P7
,R2
,F1,F9,C8,C2,D7,D3,
A9,C1,C3,C7,C9,E9,
G1,G3,G7,G9
A7,B2,B8,D2,D8,E7,
F2,F8,H2,H8
G8,G2,H7,H3,H1,H9
BALL NUMBER
A2,E2,R3,R7,R8
A1,E1,J9,M9,R1
A3,E3,J3,N1,P9
D1,D9,B1,B9
K7,L7,K3
L2,L3,L1
F7,E8
B7,A8
B3,F3
J8,K8
K9
L8
K2
J2
J7
J1
RAS , CAS ,
DQ0−DQ15
SYMBOL
BA0−BA2
A0−A12
UDQS,
LDQS,
UDQS
V
LDQS
V
V
V
V
UDM
CLK,
ODT
LDM
CLK
CKE
V
V
WE
SSDL
CS
NC
DDQ
SSQ
REF
DDL
DD
SS
On Die Termination
Reference Voltage
DLL Power Supply
LOW Data Strobe
DQ Power Supply
Command Inputs
Differential Clock
Input Data Mask
UP Data Strobe
No Connection
Power Supply
Clock Enable
FUNCTION
DLL Ground
Bank Select
Chip Select
DQ Ground
Data Input
Address
/ Output
Ground
Control
Inputs
Provide the row address for active commands, and the column
address and Auto-precharge bit for Read/Write commands to select
one location out of the memory array in the respective bank.
Row address: A0−A12.
Column address: A0−A9. (A10 is used for Auto-precharge)
BA0−BA2 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
Bi-directional data bus.
ODT (registered HIGH) enables termination resistance internal to the
DDR2 SDRAM.
Data Strobe for Lower Byte: Output with read data, input with write
data for source synchronous operation. Edge-aligned with read data,
center-aligned with write data. LDQS corresponds to the data on
DQ0−DQ7. LDQS is only used when differential data strobe mode
is enabled via the control bit at EMR (1)[A10 EMRS command].
Data Strobe for Upper Byte: Output with read data, input with write
data for source synchronous operation. Edge-aligned with read data,
center-aligned with write data. UDQS corresponds to the data on
DQ8−DQ15. UDQS is only used when differential data strobe mode
is enabled via the control bit at EMR (1)[A10 EMRS command].
All commands are masked when CS is registered HIGH
provides for external bank selection on systems with multiple ranks.
entered.
DM is an input mask signal for write data. Input data is masked when
DM is sampled high coincident with that input data during a Write
access. DM is sampled on both edges of DQS. Although DM pins are
input only, the DM loading matches the DQ and DQS loading.
CLK and CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK
and negative edge of CLK . Output (read) data is referenced to the
crossings of CLK and CLK (both directions of crossing).
CKE (registered HIGH) activates and CKE (registered LOW)
deactivates clocking circuitry on the DDR2 SDRAM.
V
Power Supply: 1.8V  0.1V.
Ground.
DQ Power Supply: 1.8V  0.1V.
DQ Ground. Isolated on the device for improved noise immunity.
No connection.
DLL Ground.
DLL Power Supply: 1.8V  0.1V.
CS is considered part of the command code.
RAS , CAS and WE (along with CS ) define the command being
- 7 -
REF
is reference voltage for inputs.
Publication Release Date: Mar. 28, 2011
DESCRIPTION
W971GG6JB
Revision A07
.
CS