W971GG6JB-25 Winbond Electronics, W971GG6JB-25 Datasheet - Page 31

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W971GG6JB-25

Manufacturer Part Number
W971GG6JB-25
Description
IC DDR2-800 SDRAM 1GB 84-WBGA
Manufacturer
Winbond Electronics
Datasheet

Specifications of W971GG6JB-25

Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
1G (64M x 16)
Speed
2.5ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
84-WBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q5804012

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8. OPERATION MODE
8.1
Notes:
1. All DDR2 SDRAM commands are defined by states of CS , RAS , CAS , WE and CKE at the rising edge of the clock.
2. Bank addresses BA [2:0] determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.
3. Burst reads or writes at BL = 4 can not be terminated or interrupted. See Burst Interrupt in section 7.5 for details.
4. V
5. Self Refresh Exit is asynchronous.
6. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the
Auto-precharge
Auto-precharge
Mode Register
Bank Activate
Precharge All
No Operation
Power Down
Power Down
Self Refresh
Self Refresh
refresh requirements outlined in section 7.9.
COMMAND
Single Bank
Mode Entry
(Extended)
Precharge
Write with
Read with
Mode Exit
REF
Deselect
Refresh
Device
Banks
Read
Write
Entry
Exit
Set
Command Truth Table
must be maintained during Self Refresh operation.
Previous
Cycle
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
CKE
Current
Cycle
H
H
H
H
H
H
H
H
X
X
H
H
H
L
L
BA2
BA1
BA0
BA
BA
BA
BA
BA
BA
BA
X
X
X
X
X
X
X
X
Column
Column
Column
Column
A12
A11
X
X
X
X
X
X
X
X
X
Row Address
- 31 -
OP Code
A10
H
H
H
X
X
X
X
X
X
X
L
L
L
Column
Column
Column
Column
A9-A0
X
X
X
X
X
X
X
X
X
Publication Release Date: Mar. 28, 2011
CS
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS
H
H
H
H
H
X
X
H
X
H
X
H
L
L
L
L
L
L
W971GG6JB
CAS
H
H
H
H
X
X
H
X
H
X
H
L
L
L
L
L
L
L
WE
H
H
H
H
H
H
H
H
H
X
X
X
X
L
L
L
L
L
Revision A07
NOTES
1,2,3
1,2,3
1,2,3
1,2,3
1,4,5
1,2
1,2
1,2
1,4
1,6
1,6
1
1
1
1

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