W971GG6JB-25 Winbond Electronics, W971GG6JB-25 Datasheet - Page 20

• Manufacturer Part Number: W971GG6JB-25
• Description: IC DDR2-800 SDRAM 1GB 84-WBGA
• Manufacturer: Winbond Electronics

Specifications of W971GG6JB-25

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 2.5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-WBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5804012

7.3
7.3.1
( CS ="L", RAS ="L", CAS ="H", WE ="H", BA0, BA1, BA2=Bank, A0 to A12 be row address)
The Bank Activate command must be applied before any Read or Write operation can be executed.
Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command
on the following clock cycle. If a Read/Write command is issued to a bank that has not satisfied the
t
Read/Write command is internally issued to the device. The additive latency value must be chosen to
assure t
been activated it must be precharged before another Bank Activate command can be applied to the
same bank. The bank active and precharge times are defined as t
minimum time interval between successive Bank Activate commands to the same bank is determined
by the RAS cycle time of the device (t
commands is t
In order to ensure that components with 8 internal memory banks do not exceed the instantaneous
current supplying capability, certain restrictions on operation of the 8 banks must be observed. There
are two rules. One for restricting the number of sequential ACT commands that can be issued and
another for allowing more time for RAS precharge for a Precharge All command. The rules are as
follows:
RCDmin


Command
Figure 12 – Bank activate command cycle: t
Address
Command Function
Sequential Bank Activation Restriction: No more than 4 banks may be activated in a rolling t
window. Converting to clocks is done by dividing t
next integer value. As an example of the rolling window, if RU{ (t
and an activate command is issued in clock N, no more than three further activate commands
may be issued at or between clock N+1 and N+9.
Precharge All Allowance: t
tn
Bank Activate Command
RCDmin
CLK
CLK
RP
specification, then additive latency must be programmed into the device to delay when the
= RU{ t
Row Addr.
RRD
Activate
Bank A
T0
Bank A
is satisfied. Additive latencies of 0, 1, 2, 3, 4, 5 and 6 are supported. Once a bank has
RAS - RAS delay time(≥ t
t
.
RCD
RP
= 1
Internal RAS - RAS delay (≥ t
/ t
CK
Col. Addr.
Post CAS
T1
Bank A
Bank A
Read
(avg) } and t
CAS - CAS delay time(t
Additive Latency delay(AL)
Bank Active (≥ t
RRD
RP
Row Addr.
)
Activate
T2
Bank B
Bank B
for a Precharge All command is equal to tn
RP
RCD
RAS
min)
CCD
is the value for a single bank precharge.
)
RC
)
Col. Addr.
Post CAS
Bank B
Bank B
T3
). The minimum time interval between Bank Activate
Read
Read Begins
- 20 -
RAS Cycle time (≥ t
RCD
= 3, AL = 2, t
FAW
Precharge
Bank A
Tn
Bank A
Addr.
[nS] by t
RC
)
Publication Release Date: Mar. 28, 2011
Bank Precharge time (≥ t
Tn+1
CK
RAS
RP
(avg)[ns], and rounding up to
FAW
= 3, t
and t
/ t
RRD
W971GG6JB
Tn+2
Precharge
CK
Bank B
Bank B
RP
Addr.
RP
RP
(avg) } is 10 clocks,
, respectively. The
= 2, t
)
+ 1 x n
CCD
Tn+3
Row Addr.
Activate
Bank A
Bank A
Revision A07
CK
= 2
, where
FAW