W971GG6JB-25 Winbond Electronics, W971GG6JB-25 Datasheet - Page 41

• Manufacturer Part Number: W971GG6JB-25
• Description: IC DDR2-800 SDRAM 1GB 84-WBGA
• Manufacturer: Winbond Electronics

Specifications of W971GG6JB-25

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 2.5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-WBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5804012

I
I
I
DD4W
DD4R
DD5B
I
I
Notes:
1. V
2. I
3. Input slew rate is specified by AC Parametric Test Condition.
4. I
5. Data Bus consists of DQ, LDM, UDM, LDQS, LDQS , UDQS and UDQS .
6. Definitions for I
7. The following I
DD6
DD7
I
and the 2X refresh option is still enabled)
DD
DD
DD3P
DD
LOW = V
HIGH = V
STABLE = inputs stable at a HIGH or LOW level
FLOATING = inputs at V
SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and
specifications are tested after the device is properly initialized.
parameters are specified with ODT disabled.
= 1.8 V
(slow) must be derated by 30 % and I
Operating Burst Read Current
All banks open, Continuous burst reads, I
BL = 4, CL = CL
t
CKE is HIGH, CS is HIGH between valid commands;
Address inputs are SWITCHING;
Data Bus inputs are SWITCHING.
Operating Burst Write Current
All banks open, Continuous burst writes;
BL = 4, CL = CL
t
CKE is HIGH, CS is HIGH between valid commands;
Address inputs are SWITCHING;
Data Bus inputs are SWITCHING.
Burst Refresh Current
t
Refresh command every t
CKE is HIGH, CS is HIGH between valid commands;
Other control and address inputs are SWITCHING;
Data bus inputs are SWITCHING.
Self Refresh Current
CKE
Other control and address inputs are FLOATING;
Data bus inputs are FLOATING. (T
Operating Bank Interleave Read Current
All bank interleaving reads, I
BL = 4, CL = CL
t
= t
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are STABLE during deselects;
Data Bus inputs are SWITCHING.
CK
CK
CK
CK
RCD(IDD)
= t
= t
= t
= t
in

≤
in
CK(IDD)
CK(IDD)
CK(IDD)
CK(IDD)
≤
0.1V; V
DD
≥
0.2 V, external clock off, CLK and CLK at 0 V;
DD
V
V
IL (ac) (max)
values must be derated (I
IH (ac) (min)
control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock)
for DQ signals not including masks or strobes.
;
; t
; t
;
, t
DDQ
RAS
RAS
RC
(IDD),
(IDD),
(IDD),
= t
= 1.8 V
REF
= t
= t
RC(IDD)
AL = 0;
AL = 0;
AL = t
RASmax(IDD)
RASmax(IDD)
= V
RFC(IDD)

RCD(IDD)
DDQ
OUT
0.1V.
, t
RRD
/2
= 0mA;
CASE
interval;
, t
, t
DD6
DD
= t
RP
RP
- 1 x t
RRD(IDD)
limits increase), when T
must be derated by 80 %. (I
= t
= t
≤
OUT
85°C)
CK(IDD)
RP(IDD)
RP(IDD)
= 0 mA;
, t
RCD
;
;
;
- 41 -
155
160
145
285
10
CASE
DD6
≥
130
135
130
225
Publication Release Date: Mar. 28, 2011
10
85°C I
will increase by this amount if T
DD2P
130
135
130
225
4
must be derated by 20 %;
W971GG6JB
120
125
120
195
10
mA
mA
mA
mA
mA
Revision A07
CASE
1,2,3,4,5,
1,2,3,4,5,
1,2,3,4,5,
1,2,3,4,5,
1,2,3,4,5,
< 85°C
6,7
6
6
6
6