W971GG6JB-25 Winbond Electronics, W971GG6JB-25 Datasheet
W971GG6JB-25
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W971GG6JB-25 Summary of contents
Page 1
... Examples of posted 7.4.2 Burst mode operation ....................................................................................................... 24 7.4.3 Burst read mode operation ............................................................................................... 25 7.4.4 Burst write mode operation .............................................................................................. 25 7.4.5 Write data mask ............................................................................................................... 26 7.5 Burst Interrupt ..................................................................................................................................... 26 8M 8 BANKS 16 BIT DDR2 SDRAM .................................................................................................................... 23 operation ...................................................................... 23 CAS - 1 - W971GG6JB Publication Release Date: Mar. 28, 2011 Revision A07 ...
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... Burst read operation: RL=5 (AL=2, CL=3, BL=4) ................................................................................ 72 10.8 Data input (write) timing ...................................................................................................................... 73 10.9 Burst write operation: RL=5 (AL=2, CL=3, WL=4, BL=4) .................................................................... 73 10.10 Seamless burst read operation and ...................................... 74 10.11 Seamless burst write operation ......................................................... 74 W971GG6JB Publication Release Date: Mar. 28, 2011 - 2 - Revision A07 ...
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... Active Power Down Mode Entry and Exit Timing ....................................................................... 84 10.30 Precharged Power Down Mode Entry and Exit Timing .............................................................. 84 10.31 Clock frequency change in precharge Power Down mode ........................................................ 85 11. PACKAGE SPECIFICATION .............................................................................................................. 86 Package Outline WBGA-84 (8x12.5 mm 12. REVISION HISTORY .......................................................................................................................... ....................................................................................................... 86 Publication Release Date: Mar. 28, 2011 - 3 - W971GG6JB Revision A07 ...
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... GENERAL DESCRIPTION The W971GG6JB bits DDR2 SDRAM, organized as 8,388,608 words 8 banks 16 bits. This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for general applications. W971GG6JB is sorted into the following speed grades: -18, -25, 25L, 25I and -3. The -18 is compliant to the DDR2-1066 (6-6-6) specification. The -25/25L/25I are compliant to the DDR2-800 (5-5-5) specification (the 25L parts which is guaranteed to support I commercial temperature, the 25I industrial grade which is guaranteed to support -40° ...
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... Min Max Max Max Max. 155 mA Max. 160 mA Max. 145 mA ≤ Max 85C) Max. 285 mA Publication Release Date: Mar. 28, 2011 - 5 - W971GG6JB DDR2-800 DDR2-800 DDR2-667 5-5-5 5-5-5 5-5-5 -25/25I 25L -3 2.5 nS 2.5 nS 2 ...
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... VDDQ D DQ10 E VSSQ LDQS F LDQS G VDDQ H DQ2 J VSSDL K RAS L CAS A11 R NC Publication Release Date: Mar. 28, 2011 - 6 - W971GG6JB 8 9 UDQS VDDQ VSSQ DQ15 DQ8 VDDQ VSSQ DQ13 VDDQ VSSQ DQ7 DQ0 VDDQ VSSQ DQ5 CLK VDD CLK ODT CS A0 VDD A4 A8 ...
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... Power Supply Ground Ground. DQ Power Supply: 1.8V 0.1V. DQ Power Supply DQ Ground DQ Ground. Isolated on the device for improved noise immunity. No Connection No connection. DLL Ground DLL Ground. DLL Power Supply: 1.8V 0.1V W971GG6JB DESCRIPTION Publication Release Date: Mar. 28, 2011 Revision A07 . CS ...
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... BLOCK DIAGRAM DECODER ROW DECODER DECODER ROW DECODER DECODER ROW DECODER DECODER ROW DECODER Publication Release Date: Mar. 28, 2011 - 8 - W971GG6JB ROW ROW ROW ROW Revision A07 ...
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... The DDR2 SDRAM is now ready for normal operation. and ODT DDQ ≤ voltage ramp DDQ during voltage ramp time to avoid DDQ DDQ TT Publication Release Date: Mar. 28, 2011 - 9 - W971GG6JB * LOW state (all other ramps from 300 DD 0.3 volts. ≥ ≥ must be DD DDL DDQ Revision A07 ...
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... V to when PRE MRS REF REF ALL MRD RP RFC t MRD DLL min 200 Cycle Reset - 10 - W971GG6JB ramps from 300 min. DD min is achieved on V must be no DDQ DDQ t IS ANY MRS EMRS EMRS CMD t t Follow OCD RFC MRD OIT Flow chart ...
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... ODT setting. A10 DLL TM CAS Latency A7 Mode 0 Normal 1 Test Write recovery for Auto-precharge A11 A10 Reserved Figure 2 – Mode Register Set (MRS W971GG6JB Address Field BT Burst Length Mode Register Burst Length A3 Burst Type Sequential Interleave CAS Latency Latency Reserved Reserved Reserved ...
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... Output Driver Impedance Control Strobe Function Matrix Output driver A1 impedance control DQS DQS DQS 0 Normal DQS DQS Hi-z 1 Reduced Figure 3 – EMR (1) Publication Release Date: Mar. 28, 2011 - 12 - W971GG6JB Address Field Extended Mode Register (1) Rtt O.I.C DLL A0 DLL Enable 0 Enable Disable 1 A3 Latency 0 0 ...
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... A5 A4 SELF A7 High Temperature Self Refresh Rate Enable 0 Disable 1 Enable* ≤ 95°C the extended Self Refresh rate must be enabled by setting bit A7 to "1" CASE Figure 4 – EMR ( W971GG6JB ) must be satisfied to MRD Address Field 1 Extended Mode Register ( Publication Release Date: Mar. 28, 2011 ...
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... BA1 BA0 A12 A11 A10 Note: 1. All bits in EMR(3) except BA0 and BA1 are reserved for future use and must be set to 0 when programming the EMR(3 Figure 5 – EMR (3) Publication Release Date: Mar. 28, 2011 - 14 - W971GG6JB A1 A0 Address Field Extended Mode Register (3) Revision A07 ...
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... ALL OK EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit End Publication Release Date: Mar. 28, 2011 - 15 - W971GG6JB EMRS: Drive(0) DQ &DQS Low; DQS High Test Need Calibration EMRS: Enter Adjust Mode BL=4 code input to all DQs ...
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... NOP 1 Increase by 1 step 0 Decrease by 1 step 1 Increase by 1 step 0 Decrease by 1 step - 16 - W971GG6JB at bit time 1, and so forth. The driver Operation Pull-down driver strength NOP (No operation) NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step Increase by 1 step Decrease by 1 step ...
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... Figure 8. NOP NOP EMRS t OIT DQs high for Drive (1) DQs low for Drive (0) OCD calibration mode exit Figure 8 – OCD Drive Mode - 17 - W971GG6JB /t should be met fixed order and is not affected T3 NOP EMRS NOP WR ...
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... Rval1 Rval2 Rval3 Input Pin Rval1 Rval2 Rval3 sw2 sw1 sw3 SSQ SSQ SSQ ,min and t MOD window for proper operation. The timings are shown MOD Publication Release Date: Mar. 28, 2011 - 18 - W971GG6JB ,max, and CKE MOD Revision A07 ...
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... Figure 11 – ODT update delay timing - t NOP NOP NOP t MOD,max Updating MOD window, until t MOD EMRS NOP NOP t MOD,max , as measured from outside MOD Publication Release Date: Mar. 28, 2011 - 19 - W971GG6JB NOP NOP t IS New setting ,max is met. MOD NOP NOP NOP AOND New setting Revision A07 ...
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... CCD Read Begins ) Bank B Bank A Bank B Post CAS Activate Precharge Read ) RAS RAS Cycle time (≥ RCD Publication Release Date: Mar. 28, 2011 - 20 - W971GG6JB and t , respectively. The RAS RP FAW (avg)[ns], and rounding (avg clocks, FAW where RP CK Tn+1 Tn+2 Tn+3 Bank A Bank B Row Addr ...
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... Self Refresh Exit Command (CKE="H", CS ="H" or CKE="H", CS ="L", RAS ="H", CAS ="H", WE ="H", BA0, BA1, BA2 A12=Don‟t Care) min) and t (min) are satisfied. RAS( RTP Publication Release Date: Mar. 28, 2011 - 21 - W971GG6JB BA1, Revision A07 ...
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... T0 T1 CLK/CLK "HIGH" CKE ≥ NOP CMD Precharge . XSRD . . REFI ≥ t RFC NOP REF REF Figure 13 – Refresh command Publication Release Date: Mar. 28, 2011 - 22 - W971GG6JB XSNR for proper operation XSRD ). NOP or Deselect RFC . XSNR ). RFC ≥ t RFC ANY NOP Revision A07 ...
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... Chapter 10) 7.4.1.1 Examples of posted Examples of a read followed by a write to the same bank where and where are shown in Figures 14 and 15, respectively. CCD operation CAS - 23 - W971GG6JB * . The page , and is a minimum of 2 clocks for RCDmin Publication Release Date: Mar. 28, 2011 Revision A07 , ...
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... Write A-Bank WL=RL-1=4 CL=3 RL=AL+CL=5 Dout0 Dout1 Dout2 Dout3 AL=0 Read Write A-Bank A-Bank WL=RL-1=2 CL=3 RL=AL+CL=3 Dout0 Dout1 Dout2 Dout3 Publication Release Date: Mar. 28, 2011 - 24 - W971GG6JB Din0 Din1 Din2 Din3 Din0 Din1 Din2 Din3 Revision A07 ...
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... The time from the completion of the burst write to bank precharge is the write recovery time (WR). (Example timing waveforms refer to 10.8 and 10.9 Data input (write) timing and Burst write operation diagram in Chapter 10) Sequential Addressing Interleave Addressing (decimal Publication Release Date: Mar. 28, 2011 - 25 - W971GG6JB (decimal Revision A07 ...
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... Minimum Write to Precharge timing BL clock after the un-interrupted burst end and not from the end of the actual burst end. (Example timing waveforms refer to 10.12 and 10.13 Burst read and write interrupt timing diagram in Chapter 10) W971GG6JB , where t starts with the rising WR WR Publication Release Date: Mar ...
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... LOW HIGH HIGH Don‟t Care Don‟t Care , clocks” after a Read command. A new bank active RTP is satisfied. RAS Publication Release Date: Mar. 28, 2011 - 27 - W971GG6JB BA0 Precharge Bank(s) LOW Bank 0 only HIGH Bank 1 only LOW Bank 2 only HIGH Bank 3 only ...
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... Auto-precharge RP ) from the previous bank activation has been satisfied. Limit) and (t Limit) diagram in Chapter 10 has been satisfied from the previous bank activation has been satisfied W971GG6JB (min) are satisfied. (Example timing ends (not at the RTP + (Example timing RTP RP CK ...
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... DD The DLL should locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down mode for proper read operation. W971GG6JB Minimum Delay between “From Command” to “To Command” BL/2 + max(RTP BL/2 + max(RTP ...
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... Clock frequency change in precharge Power Down mode diagram in Chapter 10) has been satisfied. Maximum power down duration is limited by CKE has been satisfied. A valid, executable CKE , t XP XARD - 30 - W971GG6JB if maximum posting of tREFI , after CKE goes HIGH. XARDS Publication Release Date: Mar. 28, 2011 Revision A07 ...
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... The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh requirements outlined in section 7.9. BA2 A12 BA1 A10 A9-A0 A11 BA0 BA Row Address Column L Column BA Column H Column BA Column L Column BA Column H Column BA OP Code Publication Release Date: Mar. 28, 2011 - 31 - W971GG6JB WE NOTES CS RAS CAS 1 1 1,2 1,2 1,2 1,2 1 1,4 H ...
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... XSRD + )” in Self Refresh and Power Down. However ODT must be driven REF Publication Release Date: Mar. 28, 2011 - 32 - W971GG6JB 3 ACTION (N) NOTES Maintain Power Down 11, 13, 15 Power Down Exit 4, 8, 11, 13 Maintain Power Down 11, 15, 16 Self Refresh Exit Active Power Down 4, 8, 10, 11, ...
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... BA, CA, A10 WRIT/WRITA H BA, RA ACT L BA, A10 PRE/PREA H X AREF/SELF L Op-Code MRS/EMRS - 33 - W971GG6JB ACTION NOTES NOP or Power down NOP or Power down ILLEGAL ILLEGAL Row activating Precharge/ Precharge all banks Auto Refresh or Self Refresh Mode/Extended register accessing NOP NOP Begin read Begin write ...
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... READ/READA H L BA, CA, A10 WRIT/WRITA H BA, RA ACT L BA, A10 PRE/PREA H X AREF/SELF L Op-Code MRS/EMRS - 34 - W971GG6JB ACTION NOTES Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP-> ...
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... READ/READA L BA, CA, A10 WRIT/WRITA H BA, RA ACT L BA, A10 PRE/PREA H X AREF/SELF L Op-Code MRS/EMRS - 35 - W971GG6JB ACTION NOTES NOP-> Bank active after t WR NOP-> Bank active after t WR ILLEGAL New write ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP-> Precharge after t WR NOP-> Precharge after t WR ...
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... READA WRITA Reading with with Auto-precharge PRE, PREA PRE, PREA PRE, PREA Precharging - 36 - W971GG6JB CKEL Refreshing CKEL CKEL Autoomatic Sequence Command Sequence Read CKEL = CKE LOW, enter Power Down CKEH = CKE HIGH, exit Power Down CKEH = CKE HIGH, exit Self Refresh ...
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... V 0 DDQ DDQ V - 0.04 V REF REF is expected to track variations in V REF (dc). REF of receiving device. REF . AC parameters are measured with V DD Publication Release Date: Mar. 28, 2011 - 37 - W971GG6JB UNIT NOTES ° UNIT NOTES ° - ° MAX. UNIT NOTES 1 ...
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... IH(ac) IL(ac) IHac ΔV ) – 100 DDQ MIN 0.125 REF -0.3 -18 MIN. MAX. 0.200 V REF 0.200 V REF SSQ - 38 - W971GG6JB NOM. MAX. UNIT NOTES Ω Ω 150 180 1 Ω and I(V IH (ac) IL (ac) – I(V ) ILac) MAX 0.3 DDQ V - 0.125 ...
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... DDQ V + 0.603 TT -13.4 13.4 must be less than 21 Ω for values )/I DDQ OH must be less than 21 Ω for values max minus a noise margin are delivered to an SSTL_18 receiver W971GG6JB MIN. MAX. UNIT 1.0 2.0 pF 0.25 pF 1.0 2.0 pF 0.25 pF 2.5 3.5 pF ...
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... Other control and address inputs are SWITCHING; Data bus inputs are SWITCHING. -18 -25/25I MAX. MAX RAS RASmin(IDD RAS RASmin(IDD ≤ 85°C) CASE 50 45 Fast PDN Exit 25 MRS(12 Slow PDN Exit 15 MRS(12 RP(IDD W971GG6JB 25L -3 UNIT NOTES MAX. MAX. 1,2,3,4, 1,2,3,4, 1,2,3,4, 1,2,3,4, 1,2,3,4, 1,2,3,4, ...
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... CASE = 0mA; OUT - CK(IDD RRD RRD(IDD) RCD 285 0.1V. /2 limits increase), when T DD CASE must be derated DD6 DD6 - 41 - W971GG6JB 130 130 120 mA 135 135 125 mA 130 130 120 225 225 195 mA ≥ 85°C I must be derated DD2P will increase by this amount if T CASE Publication Release Date: Mar ...
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... CK(IDD) t 11.25 RCD(IDD) t 11.25 RP(IDD) t 51.25 RC(IDD RASmin(IDD) t 70000 RASmax(IDD RRD(IDD)-2KB t 45 FAW(IDD)-2KB t 127.5 RFC(IDD) DDR2-800 (-25/25L/25I) 5-5 2.5 12.5 12.5 52.5 40 70000 10 45 127 W971GG6JB DDR2-667 (-3) UNIT 5-5-5 5 tCK 70000 127.5 nS Publication Release Date: Mar. 28, 2011 Revision A07 ...
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... CK(avg) 0.45 0.45 -350 -325 7.5 7.5 125 200 325 325 0.6 -0.25 0.2 0.2 0.35 0.35 Publication Release Date: Mar. 28, 2011 - 43 - W971GG6JB 25 6-6-6 UNIT NOTES MAX. 70000 nS 4,23 μS 7.8 5 μS 3.9 5,6 ...
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... CL(abs) QHS RFC 200 AC,min t AC,min + 2 2.5 t AC,min t AC,min + CK(avg) Publication Release Date: Mar. 28, 2011 - 44 - W971GG6JB 25 6-6-6 UNITS NOTES MAX. t CK(avg) 0 CK(avg) 1.1 t 14,36 CK(avg) 0.6 t 14,37 CK(avg) 16,27,29, pS 41,42,44 17,27,29, pS 41,42,44 16,27,29, pS 41,42,44 17,27,29, ...
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... RP 7.5 7.5 175 250 375 375 0.6 -0.25 0.25 0.2 0.2 0.35 0. W971GG6JB DDR2-667 (-3) 25 UNITS NOTES 5-5-5 MIN. MAX. 70000 nS 4,23 127.5 nS μS 7.8 ...
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... AC,min + 2 AC,min + AC,max 1 CK(avg) IS CK(avg) Publication Release Date: Mar. 28, 2011 - 46 - W971GG6JB 25 UNITS NOTES MAX. t CK(avg) 0 CK(avg) 1.1 t 14,36 CK(avg) 0.6 t 14,37 CK(avg) 16,27,29, pS 41,42,44 17,27,29, pS 41,42,44 16,27,29, pS 41,42,44 17,27,29, pS 41,42,44 t CK(avg) t ...
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... Logic levels V levels REF t IS(ref) – Differential input waveform timing – tIS and tIH Figure 17 VTT = VDDQ/2 25Ω IH(base) IH(base) IS(base IH(ref) IS(ref) IH(ref W971GG6JB V DDQ V min IH(ac) V min IH(dc) V REF(dc) V max IL(dc) V max IL(ac Publication Release Date: Mar. 28, 2011 Revision A07 ...
Page 48
... DQS slew rate is not equal to 2.0 V/nS, then the baseline values must be derated by adding the values from table of DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential data strobe (page 60). VTT + 2x mV VTT + x mV tLZ tRPRE begin point VTT - x mV VTT - tLZ,tRPRE begin point = Publication Release Date: Mar. 28, 2011 - 48 - W971GG6JB Revision A07 ...
Page 49
... WR [nCK] + tnRP [nCK {tRP [pS] / tCK(avg) [pS] }, where WR is the value programmed in the mode register set and RU stands for round up. Example: For DDR2-1066 6-6-6 at tCK(avg) = 1.875 nS with WR programmed to 8 nCK, tDAL = 8 + RU{11. 1.875 nS} [nCK [nCK [nCK DH(base) DS(base) DH(base DH(ref) DS(ref) DH(ref W971GG6JB V DDQ V min IH(ac) V min IH(dc) V REF(dc) V max IL(dc) V max IL(ac) ...
Page 50
... That is, these parameters should be met whether clock jitter is present or not. 29. These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U)DQS/ DQS ) crossing. W971GG6JB WE , ODT, BA0, A0, A1, etc.) Publication Release Date: Mar ...
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... N = 200 N tCL / (N × tCK(avg)) j where N = 200 Publication Release Date: Mar. 28, 2011 - 51 - W971GG6JB DDR2-800 DDR2-1066 UNIT MIN. MAX. MIN. MAX. -100 100 - - -200 200 -180 180 pS -160 160 -160 ...
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... R(2per) for tER R(3per) for tER R(4per) for tER R(5per) – for tER R(6 10per) – for tER R(11 Publication Release Date: Mar. 28, 2011 - 52 - W971GG6JB 50per) Revision A07 ...
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... Publication Release Date: Mar. 28, 2011 - 53 - W971GG6JB MAX UNIT pS pS tJIT(duty),max pS tJIT(duty),max Revision A07 ...
Page 54
... Timings are specified with DQs and DM input slew rate of 1.0V/nS. 42. Timings are specified with CLK/ CLK differential slew rate of 2.0 V/nS. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/nS in differential strobe mode. W971GG6JB Publication Release Date: Mar. 28, 2011 - 54 - ...
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... W971GG6JB 1.0 V/nS Unit ΔtIS ΔtIH +210 +154 pS +203 +149 pS +193 +143 pS +180 +135 pS +160 +105 pS +127 +81 pS +60 +60 pS +55 ...
Page 56
... V max IL(dc) V max IL(ac Δ REF(dc) IL(ac)max Setup Slew Rate = Falling Signal Δ TF Figure 20 – Illustration of nominal slew rate for t W971GG6JB nominal slew rate V Δ IH(ac)min Setup Slew Rate = Rising Signal Δ IS Publication Release Date: Mar. 28, 2011 - REF ...
Page 57
... Setup Slew Rate Falling Signal = Figure 21 – Illustration of tangent line for nominal line tangent tangent line Δ TR tangent line[V Setup Slew Rate Rising Signal = - V ] REF(dc) IL(ac)max Δ TF Publication Release Date: Mar. 28, 2011 - 57 - W971GG6JB t IH line REF region - V ] IH(ac)min REF(dc) Δ Revision A07 ...
Page 58
... IL(ac Hold Slew Rate REF(dc) Rising Signal = Δ TR Figure 22 – Illustration of nominal slew rate for nominal slew rate region Δ TR Hold Slew Rate IL(dc)max Falling Signal = Publication Release Date: Mar. 28, 2011 - 58 - W971GG6JB t IH REF Δ IH(dc)min REF(dc) Δ Revision A07 ...
Page 59
... Rising Signal Figure 23 – Illustration of tangent line for tangent line tangent line nominal line Δ REF(dc) IL(ac)max Δ TR tangent line[V Hold Slew Rate Falling Signal = Publication Release Date: Mar. 28, 2011 - 59 - W971GG6JB t IH nominal line REF region Δ IH(dc)min REF(dc) Δ Revision A07 ...
Page 60
... These values are typically not subject to production test. They are verified by design and characterization. the entire table) DQS Differential Slew Rate DQS/ 1.8 V/nS 1.6 V/nS 1 - -10 - - Publication Release Date: Mar. 28, 2011 - 60 - W971GG6JB 1.2 V/nS 1.0 V/nS 0 -47 14 -35 26 -23 38 -11 -89 -12 -77 0 -65 12 -53 - -52 -140 -40 -128 -28 -116 Revision A07 - - ...
Page 61
... DQS - VTT = VDDQ/2 25Ω differential mode, these timing relationships are measured relative to the REF DQS . This distinction in timing methods is guaranteed by design and characterization W971GG6JB = - 500 mV and DQS - DQS DQS , must be tied externally Publication Release Date: Mar. 28, 2011 Revision A07 DQS ...
Page 62
... REF(dc) IL(ac)max = Falling Signal Δ TF Figure 24 – Illustration of nominal slew rate for tDS (differential DQS, DQS ) nominal slew rate nominal slew rate Δ TR Setup Slew Rate = Rising Signal Publication Release Date: Mar. 28, 2011 - 62 - W971GG6JB REF region IH(ac)min REF(dc) Δ TR Revision A07 ...
Page 63
... Falling Signal = Figure 25 – Illustration of tangent line for tDS (differential DQS, DQS ) nominal line tangent line tangent line Δ TR Setup Slew Rate tangent line[V = Rising Signal - V ] REF(dc) IL(ac)max Δ TF Publication Release Date: Mar. 28, 2011 - 63 - W971GG6JB REF region - V ] IH(ac)min REF(dc) Δ TR Revision A07 ...
Page 64
... REF(dc) Rising Signal = Δ TR Figure 26 – Illustration of nominal slew rate for tDH (differential DQS, DQS ) nominal slew rate nominal Δ TR Hold Slew Rate IL(dc)max Falling Signal = Publication Release Date: Mar. 28, 2011 - 64 - W971GG6JB t DH REF region Δ IH(dc)min REF(dc) Δ TF Revision A07 ...
Page 65
... Figure 27 – Illustration tangent line for tDH (differential DQS, DQS ) tangent tangent line nominal line Δ REF(dc) IL(ac)max tangent line [V Hold Slew Rate = Falling Signal Publication Release Date: Mar. 28, 2011 - 65 - W971GG6JB t DH nominal line line REF region Δ IH(dc)min REF(dc) Δ TF Revision A07 ...
Page 66
... OX (ac) V DDQ V min IH(ac) V min IH(dc) V REF V max V IL(dc max IL(ac ΔTR V min - V IH(ac) REF Rising Slew = Δ W971GG6JB VALUE UNIT NOTES 0 DDQ 1.0 V 1.0 V/ MAX. UNIT NOTES VDDQ + 0.6 V 0.5 x VDDQ + 0.175 V 0.5 x VDDQ + 0.125 V V DDQ Crossing point SSQ Publication Release Date: Mar ...
Page 67
... DDR2-1066 0.9 0.9 0.5 0.5 SS DDR2-1066 0.9 0.9 0.19 0.19 SSQ Maximum Amplitude /V DD DDQ /V SS SSQ Maximum Amplitude Time (nS W971GG6JB DDR2-800 DDR2-667 UNIT 0.9 0.9 V 0.9 0.9 V 0.66 0.8 V-nS 0.66 0.8 V-nS DDR2-800 DDR2-667 UNIT 0.9 0.9 0.9 0.9 ...
Page 68
... TIMING WAVEFORMS 10.1 Command Input Timing CLK CLK CS RAS CAS WE A0~A12 BA0~BA2 Refer to the Command Truth Table Publication Release Date: Mar. 28, 2011 - 68 - W971GG6JB Revision A07 ...
Page 69
... IH(ac) ODT t AOND Internal Term Res. 10.3 ODT Timing for Power Down Mode T0 T1 CLK CLK CKE IH(ac) ODT Internal Term Res. t AONPD(min) t AONPD(max IL(ac) t AOFD AON(min) t AOF(min) t AON(max IL(ac) t AOFPD(max) t AOFPD(min W971GG6JB AOF(max Publication Release Date: Mar. 28, 2011 Revision A07 ...
Page 70
... V IL(ac AOFPD(max AOND IH(ac) t AONPD(max) Publication Release Date: Mar. 28, 2011 - 70 - W971GG6JB Active & Standby mode timings to be applied Power Down mode timings to be applied Active & Standby mode timings to be applied R TT Power Down mode timings to be applied R TT Revision A07 ...
Page 71
... AXPD t IS ODT V IL(ac) Internal Term Res ODT V IL(ac) Internal R TT Term Res IH(ac) ODT Internal Term Res IH(ac) ODT Internal Term Res. t AONPD(max) Publication Release Date: Mar. 28, 2011 - 71 - W971GG6JB T9 T10 AOFD t AOFPD(max) R RTT TT t AOND R TT Revision A07 ...
Page 72
... T1 T2 CLK/CLK Posted CAS CMD NOP NOP READ A DQS, DQS DQ DQSmax NOP NOP NOP NOP NOP NOP NOP NOP Dout - 72 - W971GG6JB t RPST DQSmax NOP NOP NOP NOP NOP NOP ≤ t DQSCK Dout Dout Dout Publication Release Date: Mar. 28, 2011 Revision A07 ...
Page 73
... NOP NOP NOP NOP t t DQSS DQSS t DSS DIN DIN DIN DQSS DQSS t t DSH DSH DIN DIN DIN W971GG6JB t WPST (dc) IH DMin V (dc NOP NOP Precharge Completion of The Burst Write t DSS ≥ DIN A3 ≥ DIN A3 Publication Release Date: Mar. 28, 2011 ...
Page 74
... The seamless burst write operation is supported by enabling a write command every other clock for operation, every four clocks for operation. This operation is allowed regardless of same or different banks as long as the banks are activated NOP NOP NOP DOUT NOP NOP NOP DIN DIN DIN W971GG6JB NOP NOP NOP DOUT DOUT DOUT DOUT DOUT DOUT NOP NOP NOP ...
Page 75
... T5 T4 NOP NOP NOP READ B Dout Dout Dout Dout Dout NOP Write B NOP NOP Din Din Din Din Din W971GG6JB NOP NOP NOP Dout Dout Dout Dout Dout Dout Dout NOP NOP NOP Din Din Din Din Din Din Din B1 B2 ...
Page 76
... Write operation with Data Mask: WL=3, AL=0, BL=4) Data Mask Timing DQS/ DQS DQ DM CLK CLK CMDMAND Write Case 1: min t DQSS DQS/DQS Case 2: max t DQSS DQS/DQS IH(ac) IH(ac IH(dc) IH(dc IL(dc) IL(dc IL(ac) IL(ac DQSS (min) DQSS (max W971GG6JB t WR Publication Release Date: Mar. 28, 2011 Revision A07 ...
Page 77
... NOP Precharge NOP NOP ≥ Dout Dout NOP NOP NOP Precharge Dout Dout A0 A1 ≥ t RTP - 77 - W971GG6JB RTP Bank A NOP NOP Activate Dout Dout A2 A3 RTP NOP NOP NOP Dout Dout Dout Dout Dout Dout Publication Release Date: Mar. 28, 2011 ...
Page 78
... DQS, DQS DQ's ≥ NOP Precharge NOP NOP ≥ Dout ≥ t RAS ≥ t RTP NOP NOP NOP Precharge RAS ≥ t RTP - 78 - W971GG6JB RTP Bank A NOP NOP Activate RP Dout Dout Dout RTP Bank A NOP NOP Activate ≥ Dout Dout Dout Dout A0 A1 ...
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... NOP NOP Dout Dout Dout A0 A1 ≥ t RAS ≥ t RTP second 4-bit prefetch NOP NOP NOP NOP DIN DIN DIN DIN W971GG6JB RTP Bank A NOP NOP Activate ≥ Dout Dout Dout Dout Dout NOP NOP Precharge Completion of the Burst Write ≥ Publication Release Date: Mar ...
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... NOP NOP NOP NOP DIN A0 DIN A1 DIN A2 DIN NOP NOP NOP NOP Dout Dout Dout A0 A1 ≥ t RTP t RTP Precharge begins here - 80 - W971GG6JB NOP NOP Precharge A Completion of the Burst Write ≥ RTP Bank A NOP NOP Activate ≥ Dout Dout Dout Dout ...
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... NOP NOP + t RTP Dout Dout RTP RP Precharge begins here =3, BL=4, t RCD NOP NOP NOP Auto-precharge begins (AL + BL/ min W971GG6JB RTP Bank A NOP NOP Activate Dout Dout A2 A3 ≤ 2clks) RTP Bank A NOP NOP NOP Activate ≥ Dout Dout Dout Dout A0 A1 ...
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... NOP NOP NOP Auto-precharge begins ≥ Limit): WL=2, WR=2, BL= NOP NOP NOP NOP Completion of the Burst Write ≥ WR DIN DIN DIN min W971GG6JB RTP ≤ 2clks Bank A NOP NOP Activate t RP min. Dout Dout Dout Dout Bank A NOP NOP Activate Auto-precharge Begins ≥ ...
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... A2 A3 ≥ IL(ac) t AOFD Self IH(ac) IH(dc) Refresh V V IL(dc) IL(ac W971GG6JB T11 Bank A NOP NOP Activate Auto-precharge Begins t RP min ≥ t XSNR ≥ t XSRD V IH(ac tIS Read Non-Read NOP NOP Command Command Publication Release Date: Mar. 28, 2011 Revision A07 =3 Tn ...
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... CMD CKE Precharge Power Down Entry T2 Tn NOP Active Power Down Exit NOP NOP NOP Precharge Power Down Exit - 84 - W971GG6JB Tn+2 Tn+1 Valid NOP NOP Command XARD IS t XARDS Tn+1 Tn+2 Valid NOP NOP Command Publication Release Date: Mar. 28, 2011 Revision A07 ...
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... X+1 Y Y+1 Y+2 NOP t Frequency change IS Occurs here Stable new clock before power down exit Publication Release Date: Mar. 28, 2011 - 85 - W971GG6JB Y+3 Y+4 z DLL NOP NOP Valid RESET 200 Clocks ODT is off during DLL RESET Revision A07 ...
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... BSC. 6.40 BSC. 0.80 BSC. 0.80 BSC. Note: 1. Ball land : 0.5mm --- 0.15 --- 0.20 0.10 --- - 86 - W971GG6JB aaa E B Ball Land Ball Opening 2. Ball opening : 0.4mm 3. PCB Ball land suggested ≤ 0.4mm Publication Release Date: Mar. 28, 2011 Revision A07 C 4X ...
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... Add notes 45, 46 and 47 for section 9.11 all AC parameters to describes of slew rate measurement 61 levels, output slew rate test load and differential data strobe Important Notice Publication Release Date: Mar. 28, 2011 - 87 - W971GG6JB DESCRIPTION -t ) from RCD RP (avg) from 0.48 (min.)/0.52 (max.) (avg) ...