W971GG6JB-25 Winbond Electronics, W971GG6JB-25 Datasheet - Page 25

• Manufacturer Part Number: W971GG6JB-25
• Description: IC DDR2-800 SDRAM 1GB 84-WBGA
• Manufacturer: Winbond Electronics

Specifications of W971GG6JB-25

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 2.5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-WBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5804012

Unlike DDR1 devices, interruption of a burst read or writes cycle during BL = 4 mode operation is
prohibited. However in case of BL = 8 mode, interruption of a burst read or write operation is limited to
two cases, reads interrupted by a read, or writes interrupted by a write. (Example timing waveforms
refer to 10.12 and 10.13 Burst read and write interrupt timing diagram in Chapter 10)
Therefore the Burst Stop command is not supported on DDR2 SDRAM devices.
7.4.3
Burst Read is initiated with a READ command. The address inputs determine the starting column
address for the burst. The delay from the start of the command to when the data from the first cell
appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is
driven LOW one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst
is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on
the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an
additive latency (AL) plus CAS Latency (CL). The CL is defined by the Mode Register Set (MRS). The
AL is defined by the Extended Mode Register EMR (1). (Example timing waveforms refer to 10.6 and
10.7 Data output (read) timing and Burst read operation diagram in Chapter 10)
7.4.4
Burst Write is initiated with a WRITE command. The address inputs determine the starting column
address for the burst. Write Latency (WL) is defined by a Read Latency (RL) minus one and is equal
to (AL + CL -1); and is the number of clocks of delay that are required from the time the write
command is registered to the clock edge associated to the first DQS strobe. A data strobe signal
(DQS) should be driven LOW (preamble) nominally half clock prior to the WL. The first data bit of the
burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble.
The t
during write cycles. The subsequent burst bit data are issued on successive edges of the DQS until
the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any additional
data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is
complete. The time from the completion of the burst write to bank precharge is the write recovery time
(WR). (Example timing waveforms refer to 10.8 and 10.9 Data input (write) timing and Burst write
operation diagram in Chapter 10)
Burst Length
DQSS
4
8
Burst read mode operation
Burst write mode operation
specification must be satisfied for each positive DQS transition to its associated clock edge
Starting Address
(A2 A1 A0)
000
001
010
011
100
101
110
111
x00
x01
x10
x11
Table 3 – Burst Length and Sequence
Sequential Addressing
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
- 25 -
(decimal)
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
Publication Release Date: Mar. 28, 2011
Interleave Addressing
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
W971GG6JB
(decimal)
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
Revision A07