W971GG6JB-25 Winbond Electronics, W971GG6JB-25 Datasheet - Page 4

• Manufacturer Part Number: W971GG6JB-25
• Description: IC DDR2-800 SDRAM 1GB 84-WBGA
• Manufacturer: Winbond Electronics

Specifications of W971GG6JB-25

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 2.5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-WBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5804012

1. GENERAL DESCRIPTION
The W971GG6JB is a 1G bits DDR2 SDRAM, organized as 8,388,608 words  8 banks  16 bits. This
device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for general
applications. W971GG6JB is sorted into the following speed grades: -18, -25, 25L, 25I and -3. The -18
is compliant to the DDR2-1066 (6-6-6) specification. The -25/25L/25I are compliant to the DDR2-800
(5-5-5) specification (the 25L parts which is guaranteed to support I
commercial temperature, the 25I industrial grade which is guaranteed to support -40°C ≤ T
95°C). The -3 is compliant to the DDR2-667 (5-5-5) specification.
All of the control and address inputs are synchronized with a pair of externally supplied differential
clocks. Inputs are latched at the cross point of differential clocks (CLK rising and CLK falling). All
I/Os are synchronized with a single ended DQS or differential DQS- DQS pair in a source
synchronous fashion.
2. FEATURES
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Power Supply: V
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and CLK )
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to both edges
of DQS
Posted CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal
quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
Packaged in WBGA 84 Ball (8X12.5 mm
DD
, V
DDQ
= 1.8 V  0.1 V
2
), using Lead free materials with RoHS compliant
- 4 -
Publication Release Date: Mar. 28, 2011
DD2P
= 7 mA and I
W971GG6JB
DD6
Revision A07
= 4 mA at
CASE
≤